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Searched refs:DDRPHYC_MR2_NWRE_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9116 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
9117 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp151fxx_cm4.h9279 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
9280 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp151axx_ca7.h9116 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
9117 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp151axx_cm4.h9082 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
9083 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp151dxx_cm4.h9082 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
9083 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp151cxx_ca7.h9313 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
9314 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp151cxx_cm4.h9279 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
9280 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp151fxx_ca7.h9313 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
9314 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp153axx_ca7.h10667 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
10668 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp153axx_cm4.h10633 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
10634 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp153cxx_ca7.h10864 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
10865 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp153cxx_cm4.h10830 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
10831 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp153dxx_ca7.h10667 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
10668 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp153dxx_cm4.h10633 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
10634 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp153fxx_ca7.h10864 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
10865 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp153fxx_cm4.h10830 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
10831 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp157axx_ca7.h10782 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
10783 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp157axx_cm4.h10748 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
10749 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp157cxx_ca7.h10979 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
10980 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp157cxx_cm4.h10945 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
10946 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp157dxx_ca7.h10782 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
10783 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp157dxx_cm4.h10748 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
10749 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp157fxx_ca7.h10979 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
10980 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */
Dstm32mp157fxx_cm4.h10945 #define DDRPHYC_MR2_NWRE_Pos (4U) macro
10946 #define DDRPHYC_MR2_NWRE_Msk (0x1UL << DDRPHYC_MR2_NWRE_Pos) /*!< 0x00000010 */