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Searched refs:DDRPHYC_MR1_QOFF_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9064 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
9065 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp151fxx_cm4.h9227 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
9228 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp151axx_ca7.h9064 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
9065 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp151axx_cm4.h9030 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
9031 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp151dxx_cm4.h9030 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
9031 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp151cxx_ca7.h9261 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
9262 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp151cxx_cm4.h9227 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
9228 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp151fxx_ca7.h9261 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
9262 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp153axx_ca7.h10615 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
10616 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp153axx_cm4.h10581 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
10582 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp153cxx_ca7.h10812 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
10813 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp153cxx_cm4.h10778 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
10779 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp153dxx_ca7.h10615 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
10616 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp153dxx_cm4.h10581 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
10582 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp153fxx_ca7.h10812 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
10813 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp153fxx_cm4.h10778 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
10779 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp157axx_ca7.h10730 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
10731 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp157axx_cm4.h10696 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
10697 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp157cxx_ca7.h10927 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
10928 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp157cxx_cm4.h10893 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
10894 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp157dxx_ca7.h10730 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
10731 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp157dxx_cm4.h10696 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
10697 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp157fxx_ca7.h10927 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
10928 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */
Dstm32mp157fxx_cm4.h10893 #define DDRPHYC_MR1_QOFF_Pos (12U) macro
10894 #define DDRPHYC_MR1_QOFF_Msk (0x1UL << DDRPHYC_MR1_QOFF_Pos) /*!< 0x00001000 */