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Searched refs:DDRPHYC_MR0_RSVD_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9027 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
9028 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
9030 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
9031 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
9032 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp151fxx_cm4.h9190 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
9191 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
9193 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
9194 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
9195 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp151axx_ca7.h9027 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
9028 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
9030 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
9031 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
9032 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp151axx_cm4.h8993 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
8994 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
8996 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
8997 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
8998 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp151dxx_cm4.h8993 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
8994 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
8996 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
8997 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
8998 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp151cxx_ca7.h9224 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
9225 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
9227 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
9228 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
9229 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp151cxx_cm4.h9190 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
9191 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
9193 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
9194 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
9195 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp151fxx_ca7.h9224 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
9225 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
9227 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
9228 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
9229 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp153axx_ca7.h10578 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
10579 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
10581 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
10582 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
10583 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp153axx_cm4.h10544 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
10545 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
10547 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
10548 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
10549 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp153cxx_ca7.h10775 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
10776 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
10778 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
10779 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
10780 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp153cxx_cm4.h10741 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
10742 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
10744 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
10745 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
10746 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp153dxx_ca7.h10578 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
10579 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
10581 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
10582 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
10583 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp153dxx_cm4.h10544 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
10545 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
10547 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
10548 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
10549 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp153fxx_ca7.h10775 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
10776 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
10778 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
10779 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
10780 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp153fxx_cm4.h10741 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
10742 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
10744 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
10745 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
10746 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp157axx_ca7.h10693 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
10694 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
10696 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
10697 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
10698 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp157axx_cm4.h10659 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
10660 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
10662 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
10663 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
10664 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp157cxx_ca7.h10890 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
10891 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
10893 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
10894 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
10895 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp157cxx_cm4.h10856 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
10857 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
10859 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
10860 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
10861 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp157dxx_ca7.h10693 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
10694 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
10696 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
10697 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
10698 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp157dxx_cm4.h10659 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
10660 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
10662 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
10663 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
10664 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp157fxx_ca7.h10890 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
10891 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
10893 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
10894 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
10895 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */
Dstm32mp157fxx_cm4.h10856 #define DDRPHYC_MR0_RSVD_Pos (13U) macro
10857 #define DDRPHYC_MR0_RSVD_Msk (0x7UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x0000E000 */
10859 #define DDRPHYC_MR0_RSVD_0 (0x1UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00002000 */
10860 #define DDRPHYC_MR0_RSVD_1 (0x2UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00004000 */
10861 #define DDRPHYC_MR0_RSVD_2 (0x4UL << DDRPHYC_MR0_RSVD_Pos) /*!< 0x00008000 */