Home
last modified time | relevance | path

Searched refs:DDRPHYC_MR0_CL_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9006 #define DDRPHYC_MR0_CL_Pos (4U) macro
9007 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
9009 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
9010 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
9011 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp151fxx_cm4.h9169 #define DDRPHYC_MR0_CL_Pos (4U) macro
9170 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
9172 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
9173 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
9174 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp151axx_ca7.h9006 #define DDRPHYC_MR0_CL_Pos (4U) macro
9007 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
9009 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
9010 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
9011 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp151axx_cm4.h8972 #define DDRPHYC_MR0_CL_Pos (4U) macro
8973 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
8975 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
8976 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
8977 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp151dxx_cm4.h8972 #define DDRPHYC_MR0_CL_Pos (4U) macro
8973 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
8975 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
8976 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
8977 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp151cxx_ca7.h9203 #define DDRPHYC_MR0_CL_Pos (4U) macro
9204 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
9206 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
9207 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
9208 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp151cxx_cm4.h9169 #define DDRPHYC_MR0_CL_Pos (4U) macro
9170 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
9172 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
9173 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
9174 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp151fxx_ca7.h9203 #define DDRPHYC_MR0_CL_Pos (4U) macro
9204 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
9206 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
9207 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
9208 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp153axx_ca7.h10557 #define DDRPHYC_MR0_CL_Pos (4U) macro
10558 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
10560 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
10561 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
10562 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp153axx_cm4.h10523 #define DDRPHYC_MR0_CL_Pos (4U) macro
10524 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
10526 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
10527 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
10528 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp153cxx_ca7.h10754 #define DDRPHYC_MR0_CL_Pos (4U) macro
10755 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
10757 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
10758 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
10759 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp153cxx_cm4.h10720 #define DDRPHYC_MR0_CL_Pos (4U) macro
10721 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
10723 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
10724 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
10725 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp153dxx_ca7.h10557 #define DDRPHYC_MR0_CL_Pos (4U) macro
10558 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
10560 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
10561 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
10562 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp153dxx_cm4.h10523 #define DDRPHYC_MR0_CL_Pos (4U) macro
10524 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
10526 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
10527 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
10528 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp153fxx_ca7.h10754 #define DDRPHYC_MR0_CL_Pos (4U) macro
10755 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
10757 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
10758 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
10759 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp153fxx_cm4.h10720 #define DDRPHYC_MR0_CL_Pos (4U) macro
10721 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
10723 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
10724 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
10725 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp157axx_ca7.h10672 #define DDRPHYC_MR0_CL_Pos (4U) macro
10673 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
10675 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
10676 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
10677 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp157axx_cm4.h10638 #define DDRPHYC_MR0_CL_Pos (4U) macro
10639 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
10641 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
10642 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
10643 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp157cxx_ca7.h10869 #define DDRPHYC_MR0_CL_Pos (4U) macro
10870 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
10872 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
10873 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
10874 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp157cxx_cm4.h10835 #define DDRPHYC_MR0_CL_Pos (4U) macro
10836 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
10838 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
10839 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
10840 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp157dxx_ca7.h10672 #define DDRPHYC_MR0_CL_Pos (4U) macro
10673 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
10675 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
10676 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
10677 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp157dxx_cm4.h10638 #define DDRPHYC_MR0_CL_Pos (4U) macro
10639 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
10641 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
10642 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
10643 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp157fxx_ca7.h10869 #define DDRPHYC_MR0_CL_Pos (4U) macro
10870 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
10872 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
10873 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
10874 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */
Dstm32mp157fxx_cm4.h10835 #define DDRPHYC_MR0_CL_Pos (4U) macro
10836 #define DDRPHYC_MR0_CL_Msk (0x7UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000070 */
10838 #define DDRPHYC_MR0_CL_0 (0x1UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000010 */
10839 #define DDRPHYC_MR0_CL_1 (0x2UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000020 */
10840 #define DDRPHYC_MR0_CL_2 (0x4UL << DDRPHYC_MR0_CL_Pos) /*!< 0x00000040 */