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Searched refs:DDRPHYC_GPR1_GPR1_18 (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9340 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp151fxx_cm4.h9503 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp151axx_ca7.h9340 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp151axx_cm4.h9306 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp151dxx_cm4.h9306 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp151cxx_ca7.h9537 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp151cxx_cm4.h9503 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp151fxx_ca7.h9537 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp153axx_ca7.h10891 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp153axx_cm4.h10857 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp153cxx_ca7.h11088 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp153cxx_cm4.h11054 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp153dxx_ca7.h10891 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp153dxx_cm4.h10857 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp153fxx_ca7.h11088 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp153fxx_cm4.h11054 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp157axx_ca7.h11006 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp157axx_cm4.h10972 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp157cxx_ca7.h11203 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp157cxx_cm4.h11169 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp157dxx_ca7.h11006 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp157dxx_cm4.h10972 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp157fxx_ca7.h11203 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro
Dstm32mp157fxx_cm4.h11169 #define DDRPHYC_GPR1_GPR1_18 (0x40000UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ macro