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Searched refs:DDRPHYC_GPR1_GPR1_10 (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9332 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp151fxx_cm4.h9495 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp151axx_ca7.h9332 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp151axx_cm4.h9298 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp151dxx_cm4.h9298 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp151cxx_ca7.h9529 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp151cxx_cm4.h9495 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp151fxx_ca7.h9529 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp153axx_ca7.h10883 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp153axx_cm4.h10849 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp153cxx_ca7.h11080 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp153cxx_cm4.h11046 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp153dxx_ca7.h10883 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp153dxx_cm4.h10849 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp153fxx_ca7.h11080 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp153fxx_cm4.h11046 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp157axx_ca7.h10998 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp157axx_cm4.h10964 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp157cxx_ca7.h11195 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp157cxx_cm4.h11161 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp157dxx_ca7.h10998 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp157dxx_cm4.h10964 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp157fxx_ca7.h11195 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro
Dstm32mp157fxx_cm4.h11161 #define DDRPHYC_GPR1_GPR1_10 (0x400UL << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ macro