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Searched refs:DDRPHYC_DXCCR_DXPDR_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h8709 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
8710 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp151fxx_cm4.h8872 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
8873 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp151axx_ca7.h8709 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
8710 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp151axx_cm4.h8675 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
8676 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp151dxx_cm4.h8675 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
8676 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp151cxx_ca7.h8906 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
8907 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp151cxx_cm4.h8872 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
8873 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp151fxx_ca7.h8906 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
8907 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp153axx_ca7.h10260 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
10261 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp153axx_cm4.h10226 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
10227 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp153cxx_ca7.h10457 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
10458 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp153cxx_cm4.h10423 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
10424 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp153dxx_ca7.h10260 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
10261 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp153dxx_cm4.h10226 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
10227 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp153fxx_ca7.h10457 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
10458 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp153fxx_cm4.h10423 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
10424 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp157axx_ca7.h10375 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
10376 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp157axx_cm4.h10341 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
10342 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp157cxx_ca7.h10572 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
10573 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp157cxx_cm4.h10538 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
10539 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp157dxx_ca7.h10375 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
10376 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp157dxx_cm4.h10341 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
10342 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp157fxx_ca7.h10572 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
10573 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
Dstm32mp157fxx_cm4.h10538 #define DDRPHYC_DXCCR_DXPDR_Pos (3U) macro
10539 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */