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Searched refs:DDRPHYC_DXCCR_DXPDR_Msk (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h8710 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
8711 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp151fxx_cm4.h8873 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
8874 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp151axx_ca7.h8710 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
8711 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp151axx_cm4.h8676 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
8677 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp151dxx_cm4.h8676 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
8677 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp151cxx_ca7.h8907 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
8908 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp151cxx_cm4.h8873 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
8874 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp151fxx_ca7.h8907 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
8908 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp153axx_ca7.h10261 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
10262 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp153axx_cm4.h10227 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
10228 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp153cxx_ca7.h10458 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
10459 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp153cxx_cm4.h10424 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
10425 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp153dxx_ca7.h10261 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
10262 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp153dxx_cm4.h10227 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
10228 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp153fxx_ca7.h10458 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
10459 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp153fxx_cm4.h10424 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
10425 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp157axx_ca7.h10376 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
10377 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp157axx_cm4.h10342 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
10343 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp157cxx_ca7.h10573 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
10574 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp157cxx_cm4.h10539 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
10540 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp157dxx_ca7.h10376 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
10377 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp157dxx_cm4.h10342 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
10343 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp157fxx_ca7.h10573 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
10574 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…
Dstm32mp157fxx_cm4.h10539 #define DDRPHYC_DXCCR_DXPDR_Msk (0x1UL << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ macro
10540 #define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver…