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Searched refs:DDRPHYC_DXCCR_DXODT_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h8700 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
8701 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp151fxx_cm4.h8863 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
8864 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp151axx_ca7.h8700 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
8701 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp151axx_cm4.h8666 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
8667 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp151dxx_cm4.h8666 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
8667 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp151cxx_ca7.h8897 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
8898 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp151cxx_cm4.h8863 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
8864 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp151fxx_ca7.h8897 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
8898 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp153axx_ca7.h10251 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
10252 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp153axx_cm4.h10217 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
10218 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp153cxx_ca7.h10448 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
10449 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp153cxx_cm4.h10414 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
10415 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp153dxx_ca7.h10251 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
10252 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp153dxx_cm4.h10217 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
10218 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp153fxx_ca7.h10448 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
10449 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp153fxx_cm4.h10414 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
10415 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp157axx_ca7.h10366 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
10367 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp157axx_cm4.h10332 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
10333 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp157cxx_ca7.h10563 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
10564 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp157cxx_cm4.h10529 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
10530 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp157dxx_ca7.h10366 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
10367 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp157dxx_cm4.h10332 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
10333 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp157fxx_ca7.h10563 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
10564 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
Dstm32mp157fxx_cm4.h10529 #define DDRPHYC_DXCCR_DXODT_Pos (0U) macro
10530 #define DDRPHYC_DXCCR_DXODT_Msk (0x1UL << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */