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Searched refs:DDRPHYC_DX3GSR1_RVPASS_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h10219 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
10220 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
10222 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
10223 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
10224 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp151fxx_cm4.h10382 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
10383 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
10385 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
10386 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
10387 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp151axx_ca7.h10219 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
10220 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
10222 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
10223 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
10224 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp151axx_cm4.h10185 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
10186 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
10188 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
10189 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
10190 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp151dxx_cm4.h10185 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
10186 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
10188 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
10189 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
10190 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp151cxx_ca7.h10416 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
10417 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
10419 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
10420 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
10421 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp151cxx_cm4.h10382 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
10383 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
10385 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
10386 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
10387 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp151fxx_ca7.h10416 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
10417 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
10419 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
10420 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
10421 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp153axx_ca7.h11770 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
11771 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
11773 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
11774 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
11775 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp153axx_cm4.h11736 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
11737 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
11739 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
11740 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
11741 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp153cxx_ca7.h11967 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
11968 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
11970 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
11971 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
11972 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp153cxx_cm4.h11933 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
11934 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
11936 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
11937 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
11938 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp153dxx_ca7.h11770 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
11771 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
11773 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
11774 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
11775 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp153dxx_cm4.h11736 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
11737 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
11739 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
11740 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
11741 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp153fxx_ca7.h11967 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
11968 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
11970 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
11971 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
11972 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp153fxx_cm4.h11933 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
11934 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
11936 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
11937 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
11938 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp157axx_ca7.h11885 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
11886 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
11888 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
11889 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
11890 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp157axx_cm4.h11851 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
11852 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
11854 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
11855 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
11856 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp157cxx_ca7.h12082 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
12083 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
12085 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
12086 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
12087 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp157cxx_cm4.h12048 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
12049 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
12051 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
12052 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
12053 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp157dxx_ca7.h11885 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
11886 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
11888 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
11889 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
11890 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp157dxx_cm4.h11851 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
11852 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
11854 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
11855 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
11856 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp157fxx_ca7.h12082 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
12083 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
12085 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
12086 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
12087 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
Dstm32mp157fxx_cm4.h12048 #define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) macro
12049 #define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
12051 #define DDRPHYC_DX3GSR1_RVPASS_0 (0x1UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
12052 #define DDRPHYC_DX3GSR1_RVPASS_1 (0x2UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
12053 #define DDRPHYC_DX3GSR1_RVPASS_2 (0x4UL << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */