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Searched refs:DDRPHYC_DX3GCR_RTTOH_Msk (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h10173 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
10174 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp151fxx_cm4.h10336 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
10337 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp151axx_ca7.h10173 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
10174 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp151axx_cm4.h10139 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
10140 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp151dxx_cm4.h10139 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
10140 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp151cxx_ca7.h10370 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
10371 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp151cxx_cm4.h10336 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
10337 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp151fxx_ca7.h10370 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
10371 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp153axx_ca7.h11724 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
11725 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp153axx_cm4.h11690 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
11691 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp153cxx_ca7.h11921 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
11922 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp153cxx_cm4.h11887 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
11888 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp153dxx_ca7.h11724 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
11725 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp153dxx_cm4.h11690 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
11691 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp153fxx_ca7.h11921 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
11922 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp153fxx_cm4.h11887 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
11888 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp157axx_ca7.h11839 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
11840 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp157axx_cm4.h11805 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
11806 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp157cxx_ca7.h12036 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
12037 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp157cxx_cm4.h12002 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
12003 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp157dxx_ca7.h11839 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
11840 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp157dxx_cm4.h11805 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
11806 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp157fxx_ca7.h12036 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
12037 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
Dstm32mp157fxx_cm4.h12002 #define DDRPHYC_DX3GCR_RTTOH_Msk (0x3UL << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ macro
12003 #define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */