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Searched refs:DDRPHYC_DX3GCR_DXPDR_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h10155 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
10156 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp151fxx_cm4.h10318 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
10319 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp151axx_ca7.h10155 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
10156 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp151axx_cm4.h10121 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
10122 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp151dxx_cm4.h10121 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
10122 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp151cxx_ca7.h10352 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
10353 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp151cxx_cm4.h10318 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
10319 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp151fxx_ca7.h10352 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
10353 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp153axx_ca7.h11706 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
11707 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp153axx_cm4.h11672 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
11673 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp153cxx_ca7.h11903 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
11904 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp153cxx_cm4.h11869 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
11870 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp153dxx_ca7.h11706 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
11707 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp153dxx_cm4.h11672 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
11673 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp153fxx_ca7.h11903 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
11904 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp153fxx_cm4.h11869 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
11870 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp157axx_ca7.h11821 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
11822 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp157axx_cm4.h11787 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
11788 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp157cxx_ca7.h12018 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
12019 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp157cxx_cm4.h11984 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
11985 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp157dxx_ca7.h11821 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
11822 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp157dxx_cm4.h11787 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
11788 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp157fxx_ca7.h12018 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
12019 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp157fxx_cm4.h11984 #define DDRPHYC_DX3GCR_DXPDR_Pos (5U) macro
11985 #define DDRPHYC_DX3GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */