Home
last modified time | relevance | path

Searched refs:DDRPHYC_DX3DQSTR_DQSDLY_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h10346 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
10347 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
10349 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
10350 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
10351 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp151fxx_cm4.h10509 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
10510 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
10512 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
10513 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
10514 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp151axx_ca7.h10346 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
10347 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
10349 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
10350 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
10351 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp151axx_cm4.h10312 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
10313 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
10315 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
10316 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
10317 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp151dxx_cm4.h10312 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
10313 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
10315 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
10316 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
10317 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp151cxx_ca7.h10543 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
10544 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
10546 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
10547 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
10548 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp151cxx_cm4.h10509 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
10510 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
10512 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
10513 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
10514 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp151fxx_ca7.h10543 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
10544 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
10546 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
10547 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
10548 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp153axx_ca7.h11897 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
11898 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
11900 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
11901 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
11902 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp153axx_cm4.h11863 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
11864 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
11866 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
11867 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
11868 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp153cxx_ca7.h12094 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
12095 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
12097 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
12098 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
12099 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp153cxx_cm4.h12060 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
12061 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
12063 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
12064 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
12065 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp153dxx_ca7.h11897 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
11898 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
11900 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
11901 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
11902 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp153dxx_cm4.h11863 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
11864 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
11866 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
11867 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
11868 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp153fxx_ca7.h12094 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
12095 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
12097 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
12098 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
12099 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp153fxx_cm4.h12060 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
12061 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
12063 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
12064 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
12065 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp157axx_ca7.h12012 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
12013 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
12015 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
12016 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
12017 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp157axx_cm4.h11978 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
11979 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
11981 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
11982 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
11983 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp157cxx_ca7.h12209 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
12210 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
12212 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
12213 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
12214 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp157cxx_cm4.h12175 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
12176 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
12178 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
12179 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
12180 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp157dxx_ca7.h12012 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
12013 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
12015 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
12016 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
12017 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp157dxx_cm4.h11978 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
11979 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
11981 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
11982 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
11983 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp157fxx_ca7.h12209 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
12210 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
12212 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
12213 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
12214 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
Dstm32mp157fxx_cm4.h12175 #define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) macro
12176 #define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
12178 #define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
12179 #define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
12180 #define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4UL << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */