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Searched refs:DDRPHYC_DX3DLLCR_MFBDLY_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h10239 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
10240 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
10242 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
10243 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
10244 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp151fxx_cm4.h10402 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
10403 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
10405 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
10406 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
10407 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp151axx_ca7.h10239 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
10240 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
10242 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
10243 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
10244 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp151axx_cm4.h10205 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
10206 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
10208 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
10209 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
10210 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp151dxx_cm4.h10205 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
10206 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
10208 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
10209 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
10210 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp151cxx_ca7.h10436 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
10437 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
10439 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
10440 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
10441 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp151cxx_cm4.h10402 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
10403 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
10405 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
10406 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
10407 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp151fxx_ca7.h10436 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
10437 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
10439 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
10440 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
10441 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp153axx_ca7.h11790 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
11791 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
11793 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
11794 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
11795 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp153axx_cm4.h11756 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
11757 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
11759 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
11760 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
11761 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp153cxx_ca7.h11987 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
11988 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
11990 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
11991 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
11992 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp153cxx_cm4.h11953 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
11954 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
11956 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
11957 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
11958 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp153dxx_ca7.h11790 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
11791 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
11793 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
11794 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
11795 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp153dxx_cm4.h11756 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
11757 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
11759 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
11760 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
11761 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp153fxx_ca7.h11987 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
11988 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
11990 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
11991 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
11992 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp153fxx_cm4.h11953 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
11954 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
11956 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
11957 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
11958 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp157axx_ca7.h11905 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
11906 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
11908 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
11909 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
11910 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp157axx_cm4.h11871 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
11872 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
11874 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
11875 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
11876 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp157cxx_ca7.h12102 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
12103 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
12105 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
12106 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
12107 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp157cxx_cm4.h12068 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
12069 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
12071 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
12072 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
12073 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp157dxx_ca7.h11905 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
11906 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
11908 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
11909 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
11910 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp157dxx_cm4.h11871 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
11872 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
11874 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
11875 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
11876 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp157fxx_ca7.h12102 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
12103 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
12105 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
12106 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
12107 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
Dstm32mp157fxx_cm4.h12068 #define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) macro
12069 #define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
12071 #define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
12072 #define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
12073 #define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4UL << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */