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Searched refs:DDRPHYC_DX2GCR_DXPDR_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9928 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
9929 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp151fxx_cm4.h10091 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
10092 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp151axx_ca7.h9928 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
9929 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp151axx_cm4.h9894 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
9895 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp151dxx_cm4.h9894 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
9895 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp151cxx_ca7.h10125 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
10126 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp151cxx_cm4.h10091 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
10092 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp151fxx_ca7.h10125 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
10126 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp153axx_ca7.h11479 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
11480 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp153axx_cm4.h11445 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
11446 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp153cxx_ca7.h11676 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
11677 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp153cxx_cm4.h11642 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
11643 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp153dxx_ca7.h11479 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
11480 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp153dxx_cm4.h11445 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
11446 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp153fxx_ca7.h11676 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
11677 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp153fxx_cm4.h11642 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
11643 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp157axx_ca7.h11594 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
11595 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp157axx_cm4.h11560 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
11561 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp157cxx_ca7.h11791 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
11792 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp157cxx_cm4.h11757 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
11758 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp157dxx_ca7.h11594 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
11595 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp157dxx_cm4.h11560 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
11561 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp157fxx_ca7.h11791 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
11792 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
Dstm32mp157fxx_cm4.h11757 #define DDRPHYC_DX2GCR_DXPDR_Pos (5U) macro
11758 #define DDRPHYC_DX2GCR_DXPDR_Msk (0x1UL << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */