Home
last modified time | relevance | path

Searched refs:DDRPHYC_DX2DQSTR_R0DGPS_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h10114 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
10115 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
10117 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
10118 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp151fxx_cm4.h10277 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
10278 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
10280 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
10281 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp151axx_ca7.h10114 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
10115 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
10117 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
10118 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp151axx_cm4.h10080 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
10081 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
10083 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
10084 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp151dxx_cm4.h10080 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
10081 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
10083 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
10084 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp151cxx_ca7.h10311 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
10312 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
10314 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
10315 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp151cxx_cm4.h10277 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
10278 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
10280 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
10281 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp151fxx_ca7.h10311 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
10312 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
10314 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
10315 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp153axx_ca7.h11665 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
11666 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
11668 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
11669 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp153axx_cm4.h11631 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
11632 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
11634 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
11635 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp153cxx_ca7.h11862 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
11863 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
11865 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
11866 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp153cxx_cm4.h11828 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
11829 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
11831 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
11832 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp153dxx_ca7.h11665 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
11666 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
11668 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
11669 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp153dxx_cm4.h11631 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
11632 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
11634 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
11635 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp153fxx_ca7.h11862 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
11863 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
11865 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
11866 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp153fxx_cm4.h11828 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
11829 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
11831 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
11832 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp157axx_ca7.h11780 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
11781 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
11783 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
11784 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp157axx_cm4.h11746 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
11747 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
11749 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
11750 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp157cxx_ca7.h11977 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
11978 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
11980 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
11981 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp157cxx_cm4.h11943 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
11944 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
11946 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
11947 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp157dxx_ca7.h11780 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
11781 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
11783 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
11784 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp157dxx_cm4.h11746 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
11747 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
11749 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
11750 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp157fxx_ca7.h11977 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
11978 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
11980 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
11981 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
Dstm32mp157fxx_cm4.h11943 #define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) macro
11944 #define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
11946 #define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
11947 #define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2UL << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */