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Searched refs:DDRPHYC_DX1GCR_R0RVSL_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9726 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
9727 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
9729 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
9730 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
9731 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp151fxx_cm4.h9889 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
9890 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
9892 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
9893 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
9894 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp151axx_ca7.h9726 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
9727 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
9729 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
9730 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
9731 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp151axx_cm4.h9692 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
9693 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
9695 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
9696 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
9697 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp151dxx_cm4.h9692 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
9693 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
9695 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
9696 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
9697 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp151cxx_ca7.h9923 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
9924 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
9926 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
9927 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
9928 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp151cxx_cm4.h9889 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
9890 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
9892 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
9893 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
9894 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp151fxx_ca7.h9923 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
9924 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
9926 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
9927 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
9928 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp153axx_ca7.h11277 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
11278 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11280 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
11281 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
11282 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp153axx_cm4.h11243 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
11244 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11246 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
11247 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
11248 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp153cxx_ca7.h11474 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
11475 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11477 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
11478 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
11479 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp153cxx_cm4.h11440 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
11441 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11443 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
11444 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
11445 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp153dxx_ca7.h11277 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
11278 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11280 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
11281 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
11282 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp153dxx_cm4.h11243 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
11244 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11246 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
11247 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
11248 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp153fxx_ca7.h11474 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
11475 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11477 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
11478 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
11479 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp153fxx_cm4.h11440 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
11441 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11443 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
11444 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
11445 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp157axx_ca7.h11392 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
11393 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11395 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
11396 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
11397 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp157axx_cm4.h11358 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
11359 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11361 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
11362 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
11363 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp157cxx_ca7.h11589 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
11590 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11592 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
11593 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
11594 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp157cxx_cm4.h11555 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
11556 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11558 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
11559 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
11560 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp157dxx_ca7.h11392 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
11393 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11395 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
11396 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
11397 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp157dxx_cm4.h11358 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
11359 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11361 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
11362 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
11363 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp157fxx_ca7.h11589 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
11590 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11592 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
11593 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
11594 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp157fxx_cm4.h11555 #define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) macro
11556 #define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11558 #define DDRPHYC_DX1GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
11559 #define DDRPHYC_DX1GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
11560 #define DDRPHYC_DX1GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */