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Searched refs:DDRPHYC_DX1GCR_DXPDD_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9698 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
9699 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp151fxx_cm4.h9861 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
9862 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp151axx_ca7.h9698 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
9699 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp151axx_cm4.h9664 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
9665 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp151dxx_cm4.h9664 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
9665 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp151cxx_ca7.h9895 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
9896 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp151cxx_cm4.h9861 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
9862 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp151fxx_ca7.h9895 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
9896 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp153axx_ca7.h11249 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
11250 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp153axx_cm4.h11215 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
11216 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp153cxx_ca7.h11446 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
11447 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp153cxx_cm4.h11412 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
11413 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp153dxx_ca7.h11249 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
11250 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp153dxx_cm4.h11215 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
11216 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp153fxx_ca7.h11446 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
11447 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp153fxx_cm4.h11412 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
11413 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp157axx_ca7.h11364 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
11365 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp157axx_cm4.h11330 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
11331 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp157cxx_ca7.h11561 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
11562 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp157cxx_cm4.h11527 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
11528 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp157dxx_ca7.h11364 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
11365 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp157dxx_cm4.h11330 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
11331 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp157fxx_ca7.h11561 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
11562 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp157fxx_cm4.h11527 #define DDRPHYC_DX1GCR_DXPDD_Pos (4U) macro
11528 #define DDRPHYC_DX1GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */