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Searched refs:DDRPHYC_DX0GCR_R0RVSL_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9499 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
9500 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
9502 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
9503 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
9504 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp151fxx_cm4.h9662 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
9663 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
9665 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
9666 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
9667 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp151axx_ca7.h9499 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
9500 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
9502 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
9503 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
9504 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp151axx_cm4.h9465 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
9466 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
9468 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
9469 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
9470 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp151dxx_cm4.h9465 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
9466 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
9468 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
9469 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
9470 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp151cxx_ca7.h9696 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
9697 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
9699 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
9700 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
9701 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp151cxx_cm4.h9662 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
9663 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
9665 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
9666 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
9667 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp151fxx_ca7.h9696 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
9697 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
9699 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
9700 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
9701 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp153axx_ca7.h11050 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
11051 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11053 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
11054 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
11055 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp153axx_cm4.h11016 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
11017 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11019 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
11020 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
11021 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp153cxx_ca7.h11247 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
11248 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11250 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
11251 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
11252 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp153cxx_cm4.h11213 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
11214 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11216 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
11217 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
11218 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp153dxx_ca7.h11050 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
11051 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11053 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
11054 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
11055 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp153dxx_cm4.h11016 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
11017 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11019 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
11020 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
11021 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp153fxx_ca7.h11247 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
11248 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11250 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
11251 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
11252 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp153fxx_cm4.h11213 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
11214 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11216 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
11217 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
11218 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp157axx_ca7.h11165 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
11166 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11168 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
11169 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
11170 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp157axx_cm4.h11131 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
11132 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11134 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
11135 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
11136 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp157cxx_ca7.h11362 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
11363 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11365 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
11366 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
11367 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp157cxx_cm4.h11328 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
11329 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11331 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
11332 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
11333 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp157dxx_ca7.h11165 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
11166 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11168 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
11169 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
11170 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp157dxx_cm4.h11131 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
11132 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11134 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
11135 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
11136 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp157fxx_ca7.h11362 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
11363 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11365 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
11366 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
11367 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
Dstm32mp157fxx_cm4.h11328 #define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) macro
11329 #define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
11331 #define DDRPHYC_DX0GCR_R0RVSL_0 (0x1UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
11332 #define DDRPHYC_DX0GCR_R0RVSL_1 (0x2UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
11333 #define DDRPHYC_DX0GCR_R0RVSL_2 (0x4UL << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */