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Searched refs:DDRPHYC_DX0GCR_DXPDD_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9471 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
9472 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp151fxx_cm4.h9634 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
9635 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp151axx_ca7.h9471 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
9472 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp151axx_cm4.h9437 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
9438 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp151dxx_cm4.h9437 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
9438 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp151cxx_ca7.h9668 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
9669 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp151cxx_cm4.h9634 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
9635 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp151fxx_ca7.h9668 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
9669 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp153axx_ca7.h11022 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
11023 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp153axx_cm4.h10988 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
10989 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp153cxx_ca7.h11219 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
11220 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp153cxx_cm4.h11185 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
11186 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp153dxx_ca7.h11022 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
11023 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp153dxx_cm4.h10988 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
10989 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp153fxx_ca7.h11219 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
11220 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp153fxx_cm4.h11185 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
11186 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp157axx_ca7.h11137 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
11138 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp157axx_cm4.h11103 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
11104 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp157cxx_ca7.h11334 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
11335 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp157cxx_cm4.h11300 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
11301 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp157dxx_ca7.h11137 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
11138 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp157dxx_cm4.h11103 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
11104 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp157fxx_ca7.h11334 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
11335 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
Dstm32mp157fxx_cm4.h11300 #define DDRPHYC_DX0GCR_DXPDD_Pos (4U) macro
11301 #define DDRPHYC_DX0GCR_DXPDD_Msk (0x1UL << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */