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Searched refs:DDRPHYC_DX0GCR_DSEN_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9480 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
9481 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
9483 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
9484 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp151fxx_cm4.h9643 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
9644 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
9646 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
9647 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp151axx_ca7.h9480 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
9481 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
9483 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
9484 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp151axx_cm4.h9446 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
9447 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
9449 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
9450 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp151dxx_cm4.h9446 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
9447 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
9449 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
9450 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp151cxx_ca7.h9677 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
9678 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
9680 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
9681 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp151cxx_cm4.h9643 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
9644 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
9646 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
9647 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp151fxx_ca7.h9677 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
9678 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
9680 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
9681 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp153axx_ca7.h11031 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
11032 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
11034 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
11035 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp153axx_cm4.h10997 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
10998 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
11000 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
11001 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp153cxx_ca7.h11228 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
11229 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
11231 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
11232 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp153cxx_cm4.h11194 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
11195 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
11197 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
11198 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp153dxx_ca7.h11031 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
11032 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
11034 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
11035 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp153dxx_cm4.h10997 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
10998 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
11000 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
11001 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp153fxx_ca7.h11228 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
11229 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
11231 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
11232 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp153fxx_cm4.h11194 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
11195 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
11197 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
11198 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp157axx_ca7.h11146 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
11147 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
11149 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
11150 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp157axx_cm4.h11112 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
11113 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
11115 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
11116 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp157cxx_ca7.h11343 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
11344 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
11346 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
11347 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp157cxx_cm4.h11309 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
11310 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
11312 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
11313 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp157dxx_ca7.h11146 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
11147 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
11149 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
11150 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp157dxx_cm4.h11112 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
11113 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
11115 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
11116 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp157fxx_ca7.h11343 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
11344 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
11346 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
11347 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
Dstm32mp157fxx_cm4.h11309 #define DDRPHYC_DX0GCR_DSEN_Pos (7U) macro
11310 #define DDRPHYC_DX0GCR_DSEN_Msk (0x3UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
11312 #define DDRPHYC_DX0GCR_DSEN_0 (0x1UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
11313 #define DDRPHYC_DX0GCR_DSEN_1 (0x2UL << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */