Home
last modified time | relevance | path

Searched refs:DDRPHYC_DX0DQTR_DQDLY4_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9624 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
9625 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
9627 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
9628 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
9629 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
9630 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp151fxx_cm4.h9787 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
9788 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
9790 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
9791 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
9792 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
9793 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp151axx_ca7.h9624 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
9625 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
9627 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
9628 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
9629 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
9630 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp151axx_cm4.h9590 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
9591 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
9593 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
9594 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
9595 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
9596 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp151dxx_cm4.h9590 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
9591 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
9593 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
9594 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
9595 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
9596 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp151cxx_ca7.h9821 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
9822 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
9824 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
9825 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
9826 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
9827 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp151cxx_cm4.h9787 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
9788 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
9790 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
9791 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
9792 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
9793 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp151fxx_ca7.h9821 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
9822 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
9824 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
9825 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
9826 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
9827 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp153axx_ca7.h11175 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
11176 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
11178 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
11179 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
11180 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
11181 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp153axx_cm4.h11141 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
11142 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
11144 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
11145 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
11146 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
11147 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp153cxx_ca7.h11372 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
11373 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
11375 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
11376 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
11377 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
11378 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp153cxx_cm4.h11338 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
11339 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
11341 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
11342 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
11343 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
11344 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp153dxx_ca7.h11175 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
11176 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
11178 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
11179 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
11180 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
11181 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp153dxx_cm4.h11141 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
11142 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
11144 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
11145 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
11146 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
11147 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp153fxx_ca7.h11372 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
11373 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
11375 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
11376 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
11377 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
11378 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp153fxx_cm4.h11338 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
11339 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
11341 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
11342 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
11343 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
11344 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp157axx_ca7.h11290 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
11291 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
11293 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
11294 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
11295 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
11296 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp157axx_cm4.h11256 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
11257 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
11259 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
11260 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
11261 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
11262 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp157cxx_ca7.h11487 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
11488 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
11490 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
11491 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
11492 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
11493 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp157cxx_cm4.h11453 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
11454 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
11456 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
11457 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
11458 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
11459 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp157dxx_ca7.h11290 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
11291 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
11293 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
11294 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
11295 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
11296 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp157dxx_cm4.h11256 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
11257 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
11259 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
11260 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
11261 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
11262 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp157fxx_ca7.h11487 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
11488 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
11490 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
11491 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
11492 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
11493 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
Dstm32mp157fxx_cm4.h11453 #define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) macro
11454 #define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFUL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
11456 #define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
11457 #define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
11458 #define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
11459 #define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8UL << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */