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Searched refs:DDRPHYC_DTPR1_TFAW_4 (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h8917 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp151fxx_cm4.h9080 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp151axx_ca7.h8917 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp151axx_cm4.h8883 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp151dxx_cm4.h8883 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp151cxx_ca7.h9114 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp151cxx_cm4.h9080 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp151fxx_ca7.h9114 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp153axx_ca7.h10468 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp153axx_cm4.h10434 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp153cxx_ca7.h10665 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp153cxx_cm4.h10631 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp153dxx_ca7.h10468 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp153dxx_cm4.h10434 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp153fxx_ca7.h10665 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp153fxx_cm4.h10631 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp157axx_ca7.h10583 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp157axx_cm4.h10549 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp157cxx_ca7.h10780 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp157cxx_cm4.h10746 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp157dxx_ca7.h10583 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp157dxx_cm4.h10549 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp157fxx_ca7.h10780 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro
Dstm32mp157fxx_cm4.h10746 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ macro