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Searched refs:DDRPHYC_DTPR1_TAOND_Msk (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h8903 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
8904 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp151fxx_cm4.h9066 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
9067 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp151axx_ca7.h8903 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
8904 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp151axx_cm4.h8869 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
8870 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp151dxx_cm4.h8869 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
8870 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp151cxx_ca7.h9100 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
9101 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp151cxx_cm4.h9066 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
9067 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp151fxx_ca7.h9100 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
9101 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp153axx_ca7.h10454 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
10455 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp153axx_cm4.h10420 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
10421 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp153cxx_ca7.h10651 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
10652 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp153cxx_cm4.h10617 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
10618 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp153dxx_ca7.h10454 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
10455 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp153dxx_cm4.h10420 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
10421 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp153fxx_ca7.h10651 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
10652 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp153fxx_cm4.h10617 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
10618 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp157axx_ca7.h10569 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
10570 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp157axx_cm4.h10535 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
10536 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp157cxx_ca7.h10766 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
10767 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp157cxx_cm4.h10732 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
10733 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp157dxx_ca7.h10569 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
10570 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp157dxx_cm4.h10535 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
10536 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp157fxx_ca7.h10766 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
10767 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
Dstm32mp157fxx_cm4.h10732 #define DDRPHYC_DTPR1_TAOND_Msk (0x3UL << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ macro
10733 #define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */