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Searched refs:DDRPHYC_DTPR0_TRCD_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h8866 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
8867 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
8869 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
8870 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
8871 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
8872 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp151fxx_cm4.h9029 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
9030 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
9032 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
9033 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
9034 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
9035 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp151axx_ca7.h8866 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
8867 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
8869 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
8870 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
8871 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
8872 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp151axx_cm4.h8832 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
8833 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
8835 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
8836 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
8837 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
8838 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp151dxx_cm4.h8832 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
8833 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
8835 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
8836 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
8837 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
8838 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp151cxx_ca7.h9063 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
9064 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
9066 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
9067 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
9068 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
9069 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp151cxx_cm4.h9029 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
9030 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
9032 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
9033 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
9034 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
9035 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp151fxx_ca7.h9063 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
9064 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
9066 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
9067 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
9068 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
9069 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp153axx_ca7.h10417 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
10418 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
10420 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
10421 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
10422 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
10423 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp153axx_cm4.h10383 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
10384 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
10386 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
10387 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
10388 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
10389 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp153cxx_ca7.h10614 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
10615 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
10617 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
10618 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
10619 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
10620 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp153cxx_cm4.h10580 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
10581 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
10583 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
10584 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
10585 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
10586 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp153dxx_ca7.h10417 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
10418 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
10420 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
10421 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
10422 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
10423 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp153dxx_cm4.h10383 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
10384 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
10386 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
10387 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
10388 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
10389 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp153fxx_ca7.h10614 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
10615 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
10617 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
10618 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
10619 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
10620 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp153fxx_cm4.h10580 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
10581 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
10583 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
10584 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
10585 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
10586 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp157axx_ca7.h10532 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
10533 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
10535 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
10536 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
10537 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
10538 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp157axx_cm4.h10498 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
10499 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
10501 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
10502 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
10503 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
10504 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp157cxx_ca7.h10729 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
10730 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
10732 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
10733 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
10734 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
10735 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp157cxx_cm4.h10695 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
10696 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
10698 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
10699 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
10700 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
10701 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp157dxx_ca7.h10532 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
10533 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
10535 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
10536 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
10537 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
10538 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp157dxx_cm4.h10498 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
10499 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
10501 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
10502 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
10503 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
10504 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp157fxx_ca7.h10729 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
10730 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
10732 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
10733 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
10734 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
10735 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
Dstm32mp157fxx_cm4.h10695 #define DDRPHYC_DTPR0_TRCD_Pos (12U) macro
10696 #define DDRPHYC_DTPR0_TRCD_Msk (0xFUL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
10698 #define DDRPHYC_DTPR0_TRCD_0 (0x1UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
10699 #define DDRPHYC_DTPR0_TRCD_1 (0x2UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
10700 #define DDRPHYC_DTPR0_TRCD_2 (0x4UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
10701 #define DDRPHYC_DTPR0_TRCD_3 (0x8UL << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */