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Searched refs:DDRPHYC_DSGCR_DQSGX_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h8752 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
8753 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
8755 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
8756 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
8757 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp151fxx_cm4.h8915 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
8916 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
8918 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
8919 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
8920 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp151axx_ca7.h8752 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
8753 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
8755 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
8756 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
8757 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp151axx_cm4.h8718 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
8719 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
8721 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
8722 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
8723 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp151dxx_cm4.h8718 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
8719 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
8721 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
8722 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
8723 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp151cxx_ca7.h8949 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
8950 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
8952 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
8953 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
8954 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp151cxx_cm4.h8915 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
8916 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
8918 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
8919 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
8920 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp151fxx_ca7.h8949 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
8950 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
8952 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
8953 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
8954 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp153axx_ca7.h10303 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
10304 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
10306 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
10307 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
10308 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp153axx_cm4.h10269 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
10270 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
10272 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
10273 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
10274 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp153cxx_ca7.h10500 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
10501 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
10503 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
10504 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
10505 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp153cxx_cm4.h10466 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
10467 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
10469 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
10470 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
10471 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp153dxx_ca7.h10303 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
10304 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
10306 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
10307 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
10308 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp153dxx_cm4.h10269 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
10270 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
10272 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
10273 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
10274 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp153fxx_ca7.h10500 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
10501 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
10503 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
10504 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
10505 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp153fxx_cm4.h10466 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
10467 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
10469 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
10470 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
10471 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp157axx_ca7.h10418 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
10419 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
10421 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
10422 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
10423 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp157axx_cm4.h10384 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
10385 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
10387 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
10388 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
10389 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp157cxx_ca7.h10615 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
10616 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
10618 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
10619 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
10620 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp157cxx_cm4.h10581 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
10582 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
10584 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
10585 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
10586 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp157dxx_ca7.h10418 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
10419 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
10421 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
10422 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
10423 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp157dxx_cm4.h10384 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
10385 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
10387 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
10388 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
10389 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp157fxx_ca7.h10615 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
10616 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
10618 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
10619 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
10620 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
Dstm32mp157fxx_cm4.h10581 #define DDRPHYC_DSGCR_DQSGX_Pos (5U) macro
10582 #define DDRPHYC_DSGCR_DQSGX_Msk (0x7UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
10584 #define DDRPHYC_DSGCR_DQSGX_0 (0x1UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
10585 #define DDRPHYC_DSGCR_DQSGX_1 (0x2UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
10586 #define DDRPHYC_DSGCR_DQSGX_2 (0x4UL << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */