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Searched refs:DDRPHYC_DSGCR_DQSGE_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h8758 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
8759 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
8761 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
8762 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
8763 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp151fxx_cm4.h8921 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
8922 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
8924 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
8925 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
8926 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp151axx_ca7.h8758 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
8759 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
8761 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
8762 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
8763 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp151axx_cm4.h8724 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
8725 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
8727 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
8728 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
8729 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp151dxx_cm4.h8724 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
8725 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
8727 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
8728 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
8729 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp151cxx_ca7.h8955 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
8956 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
8958 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
8959 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
8960 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp151cxx_cm4.h8921 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
8922 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
8924 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
8925 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
8926 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp151fxx_ca7.h8955 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
8956 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
8958 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
8959 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
8960 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp153axx_ca7.h10309 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
10310 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
10312 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
10313 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
10314 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp153axx_cm4.h10275 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
10276 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
10278 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
10279 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
10280 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp153cxx_ca7.h10506 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
10507 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
10509 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
10510 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
10511 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp153cxx_cm4.h10472 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
10473 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
10475 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
10476 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
10477 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp153dxx_ca7.h10309 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
10310 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
10312 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
10313 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
10314 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp153dxx_cm4.h10275 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
10276 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
10278 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
10279 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
10280 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp153fxx_ca7.h10506 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
10507 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
10509 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
10510 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
10511 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp153fxx_cm4.h10472 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
10473 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
10475 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
10476 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
10477 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp157axx_ca7.h10424 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
10425 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
10427 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
10428 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
10429 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp157axx_cm4.h10390 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
10391 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
10393 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
10394 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
10395 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp157cxx_ca7.h10621 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
10622 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
10624 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
10625 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
10626 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp157cxx_cm4.h10587 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
10588 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
10590 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
10591 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
10592 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp157dxx_ca7.h10424 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
10425 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
10427 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
10428 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
10429 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp157dxx_cm4.h10390 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
10391 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
10393 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
10394 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
10395 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp157fxx_ca7.h10621 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
10622 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
10624 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
10625 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
10626 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
Dstm32mp157fxx_cm4.h10587 #define DDRPHYC_DSGCR_DQSGE_Pos (8U) macro
10588 #define DDRPHYC_DSGCR_DQSGE_Msk (0x7UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
10590 #define DDRPHYC_DSGCR_DQSGE_0 (0x1UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
10591 #define DDRPHYC_DSGCR_DQSGE_1 (0x2UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
10592 #define DDRPHYC_DSGCR_DQSGE_2 (0x4UL << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */