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Searched refs:DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h6047 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
6048 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp151fxx_cm4.h6210 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
6211 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp151axx_ca7.h6047 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
6048 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp151axx_cm4.h6013 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
6014 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp151dxx_cm4.h6013 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
6014 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp151cxx_ca7.h6244 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
6245 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp151cxx_cm4.h6210 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
6211 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp151fxx_ca7.h6244 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
6245 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp153axx_ca7.h7598 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
7599 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp153axx_cm4.h7564 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
7565 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp153cxx_ca7.h7795 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
7796 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp153cxx_cm4.h7761 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
7762 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp153dxx_ca7.h7598 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
7599 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp153dxx_cm4.h7564 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
7565 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp153fxx_ca7.h7795 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
7796 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp153fxx_cm4.h7761 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
7762 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp157axx_ca7.h7713 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
7714 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp157axx_cm4.h7679 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
7680 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp157cxx_ca7.h7910 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
7911 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp157cxx_cm4.h7876 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
7877 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp157dxx_ca7.h7713 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
7714 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp157dxx_cm4.h7679 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
7680 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp157fxx_ca7.h7910 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
7911 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…
Dstm32mp157fxx_cm4.h7876 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) macro
7877 #define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1UL << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!<…