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Searched refs:DDRCTRL_DRAMTMG5_T_CKE_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h6520 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
6521 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
6523 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
6524 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
6525 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
6526 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
6527 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp151fxx_cm4.h6683 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
6684 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
6686 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
6687 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
6688 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
6689 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
6690 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp151axx_ca7.h6520 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
6521 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
6523 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
6524 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
6525 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
6526 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
6527 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp151axx_cm4.h6486 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
6487 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
6489 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
6490 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
6491 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
6492 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
6493 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp151dxx_cm4.h6486 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
6487 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
6489 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
6490 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
6491 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
6492 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
6493 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp151cxx_ca7.h6717 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
6718 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
6720 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
6721 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
6722 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
6723 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
6724 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp151cxx_cm4.h6683 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
6684 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
6686 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
6687 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
6688 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
6689 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
6690 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp151fxx_ca7.h6717 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
6718 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
6720 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
6721 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
6722 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
6723 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
6724 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp153axx_ca7.h8071 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
8072 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
8074 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
8075 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
8076 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
8077 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
8078 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp153axx_cm4.h8037 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
8038 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
8040 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
8041 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
8042 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
8043 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
8044 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp153cxx_ca7.h8268 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
8269 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
8271 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
8272 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
8273 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
8274 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
8275 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp153cxx_cm4.h8234 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
8235 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
8237 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
8238 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
8239 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
8240 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
8241 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp153dxx_ca7.h8071 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
8072 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
8074 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
8075 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
8076 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
8077 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
8078 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp153dxx_cm4.h8037 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
8038 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
8040 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
8041 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
8042 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
8043 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
8044 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp153fxx_ca7.h8268 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
8269 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
8271 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
8272 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
8273 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
8274 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
8275 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp153fxx_cm4.h8234 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
8235 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
8237 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
8238 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
8239 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
8240 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
8241 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp157axx_ca7.h8186 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
8187 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
8189 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
8190 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
8191 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
8192 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
8193 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp157axx_cm4.h8152 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
8153 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
8155 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
8156 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
8157 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
8158 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
8159 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp157cxx_ca7.h8383 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
8384 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
8386 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
8387 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
8388 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
8389 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
8390 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp157cxx_cm4.h8349 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
8350 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
8352 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
8353 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
8354 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
8355 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
8356 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp157dxx_ca7.h8186 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
8187 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
8189 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
8190 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
8191 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
8192 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
8193 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp157dxx_cm4.h8152 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
8153 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
8155 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
8156 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
8157 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
8158 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
8159 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp157fxx_ca7.h8383 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
8384 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
8386 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
8387 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
8388 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
8389 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
8390 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
Dstm32mp157fxx_cm4.h8349 #define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) macro
8350 #define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FUL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
8352 #define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
8353 #define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
8354 #define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
8355 #define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
8356 #define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10UL << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */