DDRCTRL_DRAMTMG2_WR2RD_Pos (reference) in projects: hal_stm32-latest

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Searched refs:DDRCTRL_DRAMTMG2_WR2RD_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
D	stm32mp151dxx_ca7.h	6413 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 6414 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6416 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6417 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6418 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6419 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6420 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6421 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp151fxx_cm4.h	6576 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 6577 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6579 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6580 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6581 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6582 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6583 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6584 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp151axx_ca7.h	6413 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 6414 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6416 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6417 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6418 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6419 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6420 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6421 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp151axx_cm4.h	6379 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 6380 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6382 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6383 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6384 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6385 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6386 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6387 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp151dxx_cm4.h	6379 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 6380 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6382 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6383 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6384 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6385 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6386 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6387 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp151cxx_ca7.h	6610 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 6611 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6613 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6614 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6615 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6616 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6617 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6618 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp151cxx_cm4.h	6576 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 6577 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6579 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6580 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6581 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6582 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6583 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6584 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp151fxx_ca7.h	6610 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 6611 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6613 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6614 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6615 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6616 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6617 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 6618 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp153axx_ca7.h	7964 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 7965 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7967 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7968 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7969 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7970 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7971 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7972 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp153axx_cm4.h	7930 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 7931 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7933 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7934 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7935 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7936 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7937 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7938 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp153cxx_ca7.h	8161 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 8162 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8164 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8165 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8166 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8167 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8168 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8169 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp153cxx_cm4.h	8127 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 8128 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8130 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8131 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8132 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8133 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8134 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8135 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp153dxx_ca7.h	7964 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 7965 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7967 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7968 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7969 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7970 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7971 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7972 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp153dxx_cm4.h	7930 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 7931 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7933 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7934 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7935 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7936 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7937 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 7938 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp153fxx_ca7.h	8161 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 8162 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8164 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8165 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8166 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8167 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8168 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8169 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp153fxx_cm4.h	8127 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 8128 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8130 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8131 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8132 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8133 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8134 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8135 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp157axx_ca7.h	8079 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 8080 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8082 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8083 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8084 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8085 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8086 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8087 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp157axx_cm4.h	8045 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 8046 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8048 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8049 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8050 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8051 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8052 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8053 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp157cxx_ca7.h	8276 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 8277 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8279 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8280 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8281 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8282 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8283 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8284 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp157cxx_cm4.h	8242 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 8243 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8245 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8246 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8247 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8248 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8249 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8250 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp157dxx_ca7.h	8079 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 8080 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8082 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8083 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8084 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8085 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8086 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8087 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp157dxx_cm4.h	8045 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 8046 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8048 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8049 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8050 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8051 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8052 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8053 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp157fxx_ca7.h	8276 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 8277 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8279 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8280 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8281 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8282 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8283 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8284 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…
D	stm32mp157fxx_cm4.h	8242 #define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) macro 8243 #define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FUL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8245 #define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8246 #define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8247 #define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8248 #define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8249 #define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /!< 0x00… 8250 #define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20UL << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00…

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