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Searched refs:DDRCTRL_DRAMTMG0_WR2PRE_5 (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h6380 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp151fxx_cm4.h6543 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp151axx_ca7.h6380 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp151axx_cm4.h6346 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp151dxx_cm4.h6346 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp151cxx_ca7.h6577 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp151cxx_cm4.h6543 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp151fxx_ca7.h6577 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp153axx_ca7.h7931 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp153axx_cm4.h7897 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp153cxx_ca7.h8128 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp153cxx_cm4.h8094 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp153dxx_ca7.h7931 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp153dxx_cm4.h7897 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp153fxx_ca7.h8128 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp153fxx_cm4.h8094 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp157axx_ca7.h8046 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp157axx_cm4.h8012 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp157cxx_ca7.h8243 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp157cxx_cm4.h8209 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp157dxx_ca7.h8046 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp157dxx_cm4.h8012 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp157fxx_ca7.h8243 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro
Dstm32mp157fxx_cm4.h8209 #define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20UL << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ macro