Home
last modified time | relevance | path

Searched refs:DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h6823 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp151fxx_cm4.h6986 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp151axx_ca7.h6823 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp151axx_cm4.h6789 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp151dxx_cm4.h6789 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp151cxx_ca7.h7020 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp151cxx_cm4.h6986 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp151fxx_ca7.h7020 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp153axx_ca7.h8374 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp153axx_cm4.h8340 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp153cxx_ca7.h8571 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp153cxx_cm4.h8537 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp153dxx_ca7.h8374 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp153dxx_cm4.h8340 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp153fxx_ca7.h8571 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp153fxx_cm4.h8537 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp157axx_ca7.h8489 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp157axx_cm4.h8455 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp157cxx_ca7.h8686 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp157cxx_cm4.h8652 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp157dxx_ca7.h8489 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp157dxx_cm4.h8455 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp157fxx_ca7.h8686 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro
Dstm32mp157fxx_cm4.h8652 #define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1UL << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) … macro