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Searched refs:DCMI_DR_BYTE3_Pos (Results 1 – 25 of 97) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l4a6xx.h7163 #define DCMI_DR_BYTE3_Pos (24U) macro
7164 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
7166 #define DCMI_DR_BYTE3_0 (0x01UL << DCMI_DR_BYTE3_Pos) /*!< 0x01000000 */
7167 #define DCMI_DR_BYTE3_1 (0x02UL << DCMI_DR_BYTE3_Pos) /*!< 0x02000000 */
7168 #define DCMI_DR_BYTE3_2 (0x04UL << DCMI_DR_BYTE3_Pos) /*!< 0x04000000 */
7169 #define DCMI_DR_BYTE3_3 (0x08UL << DCMI_DR_BYTE3_Pos) /*!< 0x08000000 */
7170 #define DCMI_DR_BYTE3_4 (0x10UL << DCMI_DR_BYTE3_Pos) /*!< 0x10000000 */
7171 #define DCMI_DR_BYTE3_5 (0x20UL << DCMI_DR_BYTE3_Pos) /*!< 0x20000000 */
7172 #define DCMI_DR_BYTE3_6 (0x40UL << DCMI_DR_BYTE3_Pos) /*!< 0x40000000 */
7173 #define DCMI_DR_BYTE3_7 (0x80UL << DCMI_DR_BYTE3_Pos) /*!< 0x80000000 */
Dstm32l496xx.h6918 #define DCMI_DR_BYTE3_Pos (24U) macro
6919 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
6921 #define DCMI_DR_BYTE3_0 (0x01UL << DCMI_DR_BYTE3_Pos) /*!< 0x01000000 */
6922 #define DCMI_DR_BYTE3_1 (0x02UL << DCMI_DR_BYTE3_Pos) /*!< 0x02000000 */
6923 #define DCMI_DR_BYTE3_2 (0x04UL << DCMI_DR_BYTE3_Pos) /*!< 0x04000000 */
6924 #define DCMI_DR_BYTE3_3 (0x08UL << DCMI_DR_BYTE3_Pos) /*!< 0x08000000 */
6925 #define DCMI_DR_BYTE3_4 (0x10UL << DCMI_DR_BYTE3_Pos) /*!< 0x10000000 */
6926 #define DCMI_DR_BYTE3_5 (0x20UL << DCMI_DR_BYTE3_Pos) /*!< 0x20000000 */
6927 #define DCMI_DR_BYTE3_6 (0x40UL << DCMI_DR_BYTE3_Pos) /*!< 0x40000000 */
6928 #define DCMI_DR_BYTE3_7 (0x80UL << DCMI_DR_BYTE3_Pos) /*!< 0x80000000 */
Dstm32l4r5xx.h6850 #define DCMI_DR_BYTE3_Pos (24U) macro
6851 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
6853 #define DCMI_DR_BYTE3_0 (0x01UL << DCMI_DR_BYTE3_Pos) /*!< 0x01000000 */
6854 #define DCMI_DR_BYTE3_1 (0x02UL << DCMI_DR_BYTE3_Pos) /*!< 0x02000000 */
6855 #define DCMI_DR_BYTE3_2 (0x04UL << DCMI_DR_BYTE3_Pos) /*!< 0x04000000 */
6856 #define DCMI_DR_BYTE3_3 (0x08UL << DCMI_DR_BYTE3_Pos) /*!< 0x08000000 */
6857 #define DCMI_DR_BYTE3_4 (0x10UL << DCMI_DR_BYTE3_Pos) /*!< 0x10000000 */
6858 #define DCMI_DR_BYTE3_5 (0x20UL << DCMI_DR_BYTE3_Pos) /*!< 0x20000000 */
6859 #define DCMI_DR_BYTE3_6 (0x40UL << DCMI_DR_BYTE3_Pos) /*!< 0x40000000 */
6860 #define DCMI_DR_BYTE3_7 (0x80UL << DCMI_DR_BYTE3_Pos) /*!< 0x80000000 */
Dstm32l4r7xx.h6936 #define DCMI_DR_BYTE3_Pos (24U) macro
6937 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
6939 #define DCMI_DR_BYTE3_0 (0x01UL << DCMI_DR_BYTE3_Pos) /*!< 0x01000000 */
6940 #define DCMI_DR_BYTE3_1 (0x02UL << DCMI_DR_BYTE3_Pos) /*!< 0x02000000 */
6941 #define DCMI_DR_BYTE3_2 (0x04UL << DCMI_DR_BYTE3_Pos) /*!< 0x04000000 */
6942 #define DCMI_DR_BYTE3_3 (0x08UL << DCMI_DR_BYTE3_Pos) /*!< 0x08000000 */
6943 #define DCMI_DR_BYTE3_4 (0x10UL << DCMI_DR_BYTE3_Pos) /*!< 0x10000000 */
6944 #define DCMI_DR_BYTE3_5 (0x20UL << DCMI_DR_BYTE3_Pos) /*!< 0x20000000 */
6945 #define DCMI_DR_BYTE3_6 (0x40UL << DCMI_DR_BYTE3_Pos) /*!< 0x40000000 */
6946 #define DCMI_DR_BYTE3_7 (0x80UL << DCMI_DR_BYTE3_Pos) /*!< 0x80000000 */
Dstm32l4s5xx.h7102 #define DCMI_DR_BYTE3_Pos (24U) macro
7103 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
7105 #define DCMI_DR_BYTE3_0 (0x01UL << DCMI_DR_BYTE3_Pos) /*!< 0x01000000 */
7106 #define DCMI_DR_BYTE3_1 (0x02UL << DCMI_DR_BYTE3_Pos) /*!< 0x02000000 */
7107 #define DCMI_DR_BYTE3_2 (0x04UL << DCMI_DR_BYTE3_Pos) /*!< 0x04000000 */
7108 #define DCMI_DR_BYTE3_3 (0x08UL << DCMI_DR_BYTE3_Pos) /*!< 0x08000000 */
7109 #define DCMI_DR_BYTE3_4 (0x10UL << DCMI_DR_BYTE3_Pos) /*!< 0x10000000 */
7110 #define DCMI_DR_BYTE3_5 (0x20UL << DCMI_DR_BYTE3_Pos) /*!< 0x20000000 */
7111 #define DCMI_DR_BYTE3_6 (0x40UL << DCMI_DR_BYTE3_Pos) /*!< 0x40000000 */
7112 #define DCMI_DR_BYTE3_7 (0x80UL << DCMI_DR_BYTE3_Pos) /*!< 0x80000000 */
Dstm32l4s7xx.h7188 #define DCMI_DR_BYTE3_Pos (24U) macro
7189 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
7191 #define DCMI_DR_BYTE3_0 (0x01UL << DCMI_DR_BYTE3_Pos) /*!< 0x01000000 */
7192 #define DCMI_DR_BYTE3_1 (0x02UL << DCMI_DR_BYTE3_Pos) /*!< 0x02000000 */
7193 #define DCMI_DR_BYTE3_2 (0x04UL << DCMI_DR_BYTE3_Pos) /*!< 0x04000000 */
7194 #define DCMI_DR_BYTE3_3 (0x08UL << DCMI_DR_BYTE3_Pos) /*!< 0x08000000 */
7195 #define DCMI_DR_BYTE3_4 (0x10UL << DCMI_DR_BYTE3_Pos) /*!< 0x10000000 */
7196 #define DCMI_DR_BYTE3_5 (0x20UL << DCMI_DR_BYTE3_Pos) /*!< 0x20000000 */
7197 #define DCMI_DR_BYTE3_6 (0x40UL << DCMI_DR_BYTE3_Pos) /*!< 0x40000000 */
7198 #define DCMI_DR_BYTE3_7 (0x80UL << DCMI_DR_BYTE3_Pos) /*!< 0x80000000 */
Dstm32l4p5xx.h7132 #define DCMI_DR_BYTE3_Pos (24U) macro
7133 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
7135 #define DCMI_DR_BYTE3_0 (0x01UL << DCMI_DR_BYTE3_Pos) /*!< 0x01000000 */
7136 #define DCMI_DR_BYTE3_1 (0x02UL << DCMI_DR_BYTE3_Pos) /*!< 0x02000000 */
7137 #define DCMI_DR_BYTE3_2 (0x04UL << DCMI_DR_BYTE3_Pos) /*!< 0x04000000 */
7138 #define DCMI_DR_BYTE3_3 (0x08UL << DCMI_DR_BYTE3_Pos) /*!< 0x08000000 */
7139 #define DCMI_DR_BYTE3_4 (0x10UL << DCMI_DR_BYTE3_Pos) /*!< 0x10000000 */
7140 #define DCMI_DR_BYTE3_5 (0x20UL << DCMI_DR_BYTE3_Pos) /*!< 0x20000000 */
7141 #define DCMI_DR_BYTE3_6 (0x40UL << DCMI_DR_BYTE3_Pos) /*!< 0x40000000 */
7142 #define DCMI_DR_BYTE3_7 (0x80UL << DCMI_DR_BYTE3_Pos) /*!< 0x80000000 */
Dstm32l4q5xx.h7372 #define DCMI_DR_BYTE3_Pos (24U) macro
7373 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
7375 #define DCMI_DR_BYTE3_0 (0x01UL << DCMI_DR_BYTE3_Pos) /*!< 0x01000000 */
7376 #define DCMI_DR_BYTE3_1 (0x02UL << DCMI_DR_BYTE3_Pos) /*!< 0x02000000 */
7377 #define DCMI_DR_BYTE3_2 (0x04UL << DCMI_DR_BYTE3_Pos) /*!< 0x04000000 */
7378 #define DCMI_DR_BYTE3_3 (0x08UL << DCMI_DR_BYTE3_Pos) /*!< 0x08000000 */
7379 #define DCMI_DR_BYTE3_4 (0x10UL << DCMI_DR_BYTE3_Pos) /*!< 0x10000000 */
7380 #define DCMI_DR_BYTE3_5 (0x20UL << DCMI_DR_BYTE3_Pos) /*!< 0x20000000 */
7381 #define DCMI_DR_BYTE3_6 (0x40UL << DCMI_DR_BYTE3_Pos) /*!< 0x40000000 */
7382 #define DCMI_DR_BYTE3_7 (0x80UL << DCMI_DR_BYTE3_Pos) /*!< 0x80000000 */
Dstm32l4r9xx.h7018 #define DCMI_DR_BYTE3_Pos (24U) macro
7019 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
7021 #define DCMI_DR_BYTE3_0 (0x01UL << DCMI_DR_BYTE3_Pos) /*!< 0x01000000 */
7022 #define DCMI_DR_BYTE3_1 (0x02UL << DCMI_DR_BYTE3_Pos) /*!< 0x02000000 */
7023 #define DCMI_DR_BYTE3_2 (0x04UL << DCMI_DR_BYTE3_Pos) /*!< 0x04000000 */
7024 #define DCMI_DR_BYTE3_3 (0x08UL << DCMI_DR_BYTE3_Pos) /*!< 0x08000000 */
7025 #define DCMI_DR_BYTE3_4 (0x10UL << DCMI_DR_BYTE3_Pos) /*!< 0x10000000 */
7026 #define DCMI_DR_BYTE3_5 (0x20UL << DCMI_DR_BYTE3_Pos) /*!< 0x20000000 */
7027 #define DCMI_DR_BYTE3_6 (0x40UL << DCMI_DR_BYTE3_Pos) /*!< 0x40000000 */
7028 #define DCMI_DR_BYTE3_7 (0x80UL << DCMI_DR_BYTE3_Pos) /*!< 0x80000000 */
Dstm32l4s9xx.h7270 #define DCMI_DR_BYTE3_Pos (24U) macro
7271 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
7273 #define DCMI_DR_BYTE3_0 (0x01UL << DCMI_DR_BYTE3_Pos) /*!< 0x01000000 */
7274 #define DCMI_DR_BYTE3_1 (0x02UL << DCMI_DR_BYTE3_Pos) /*!< 0x02000000 */
7275 #define DCMI_DR_BYTE3_2 (0x04UL << DCMI_DR_BYTE3_Pos) /*!< 0x04000000 */
7276 #define DCMI_DR_BYTE3_3 (0x08UL << DCMI_DR_BYTE3_Pos) /*!< 0x08000000 */
7277 #define DCMI_DR_BYTE3_4 (0x10UL << DCMI_DR_BYTE3_Pos) /*!< 0x10000000 */
7278 #define DCMI_DR_BYTE3_5 (0x20UL << DCMI_DR_BYTE3_Pos) /*!< 0x20000000 */
7279 #define DCMI_DR_BYTE3_6 (0x40UL << DCMI_DR_BYTE3_Pos) /*!< 0x40000000 */
7280 #define DCMI_DR_BYTE3_7 (0x80UL << DCMI_DR_BYTE3_Pos) /*!< 0x80000000 */
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f207xx.h5802 #define DCMI_DR_BYTE3_Pos (24U) macro
5803 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
Dstm32f217xx.h5952 #define DCMI_DR_BYTE3_Pos (24U) macro
5953 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f407xx.h5801 #define DCMI_DR_BYTE3_Pos (24U) macro
5802 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
Dstm32f427xx.h5892 #define DCMI_DR_BYTE3_Pos (24U) macro
5893 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
Dstm32f446xx.h5969 #define DCMI_DR_BYTE3_Pos (24U) macro
5970 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
Dstm32f417xx.h5980 #define DCMI_DR_BYTE3_Pos (24U) macro
5981 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
Dstm32f429xx.h5951 #define DCMI_DR_BYTE3_Pos (24U) macro
5952 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
Dstm32f439xx.h6138 #define DCMI_DR_BYTE3_Pos (24U) macro
6139 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
Dstm32f437xx.h6084 #define DCMI_DR_BYTE3_Pos (24U) macro
6085 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f750xx.h6233 #define DCMI_DR_BYTE3_Pos (24U) macro
6234 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
Dstm32f745xx.h5990 #define DCMI_DR_BYTE3_Pos (24U) macro
5991 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
Dstm32f756xx.h6233 #define DCMI_DR_BYTE3_Pos (24U) macro
6234 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
Dstm32f746xx.h6045 #define DCMI_DR_BYTE3_Pos (24U) macro
6046 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
Dstm32f765xx.h6445 #define DCMI_DR_BYTE3_Pos (24U) macro
6446 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
Dstm32f777xx.h6727 #define DCMI_DR_BYTE3_Pos (24U) macro
6728 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */

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