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Searched refs:DCMI_DR_BYTE2_Pos (Results 1 – 25 of 97) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l4a6xx.h7152 #define DCMI_DR_BYTE2_Pos (16U) macro
7153 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
7155 #define DCMI_DR_BYTE2_0 (0x01UL << DCMI_DR_BYTE2_Pos) /*!< 0x00010000 */
7156 #define DCMI_DR_BYTE2_1 (0x02UL << DCMI_DR_BYTE2_Pos) /*!< 0x00020000 */
7157 #define DCMI_DR_BYTE2_2 (0x04UL << DCMI_DR_BYTE2_Pos) /*!< 0x00040000 */
7158 #define DCMI_DR_BYTE2_3 (0x08UL << DCMI_DR_BYTE2_Pos) /*!< 0x00080000 */
7159 #define DCMI_DR_BYTE2_4 (0x10UL << DCMI_DR_BYTE2_Pos) /*!< 0x00100000 */
7160 #define DCMI_DR_BYTE2_5 (0x20UL << DCMI_DR_BYTE2_Pos) /*!< 0x00200000 */
7161 #define DCMI_DR_BYTE2_6 (0x40UL << DCMI_DR_BYTE2_Pos) /*!< 0x00400000 */
7162 #define DCMI_DR_BYTE2_7 (0x80UL << DCMI_DR_BYTE2_Pos) /*!< 0x00800000 */
Dstm32l496xx.h6907 #define DCMI_DR_BYTE2_Pos (16U) macro
6908 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
6910 #define DCMI_DR_BYTE2_0 (0x01UL << DCMI_DR_BYTE2_Pos) /*!< 0x00010000 */
6911 #define DCMI_DR_BYTE2_1 (0x02UL << DCMI_DR_BYTE2_Pos) /*!< 0x00020000 */
6912 #define DCMI_DR_BYTE2_2 (0x04UL << DCMI_DR_BYTE2_Pos) /*!< 0x00040000 */
6913 #define DCMI_DR_BYTE2_3 (0x08UL << DCMI_DR_BYTE2_Pos) /*!< 0x00080000 */
6914 #define DCMI_DR_BYTE2_4 (0x10UL << DCMI_DR_BYTE2_Pos) /*!< 0x00100000 */
6915 #define DCMI_DR_BYTE2_5 (0x20UL << DCMI_DR_BYTE2_Pos) /*!< 0x00200000 */
6916 #define DCMI_DR_BYTE2_6 (0x40UL << DCMI_DR_BYTE2_Pos) /*!< 0x00400000 */
6917 #define DCMI_DR_BYTE2_7 (0x80UL << DCMI_DR_BYTE2_Pos) /*!< 0x00800000 */
Dstm32l4r5xx.h6839 #define DCMI_DR_BYTE2_Pos (16U) macro
6840 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
6842 #define DCMI_DR_BYTE2_0 (0x01UL << DCMI_DR_BYTE2_Pos) /*!< 0x00010000 */
6843 #define DCMI_DR_BYTE2_1 (0x02UL << DCMI_DR_BYTE2_Pos) /*!< 0x00020000 */
6844 #define DCMI_DR_BYTE2_2 (0x04UL << DCMI_DR_BYTE2_Pos) /*!< 0x00040000 */
6845 #define DCMI_DR_BYTE2_3 (0x08UL << DCMI_DR_BYTE2_Pos) /*!< 0x00080000 */
6846 #define DCMI_DR_BYTE2_4 (0x10UL << DCMI_DR_BYTE2_Pos) /*!< 0x00100000 */
6847 #define DCMI_DR_BYTE2_5 (0x20UL << DCMI_DR_BYTE2_Pos) /*!< 0x00200000 */
6848 #define DCMI_DR_BYTE2_6 (0x40UL << DCMI_DR_BYTE2_Pos) /*!< 0x00400000 */
6849 #define DCMI_DR_BYTE2_7 (0x80UL << DCMI_DR_BYTE2_Pos) /*!< 0x00800000 */
Dstm32l4r7xx.h6925 #define DCMI_DR_BYTE2_Pos (16U) macro
6926 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
6928 #define DCMI_DR_BYTE2_0 (0x01UL << DCMI_DR_BYTE2_Pos) /*!< 0x00010000 */
6929 #define DCMI_DR_BYTE2_1 (0x02UL << DCMI_DR_BYTE2_Pos) /*!< 0x00020000 */
6930 #define DCMI_DR_BYTE2_2 (0x04UL << DCMI_DR_BYTE2_Pos) /*!< 0x00040000 */
6931 #define DCMI_DR_BYTE2_3 (0x08UL << DCMI_DR_BYTE2_Pos) /*!< 0x00080000 */
6932 #define DCMI_DR_BYTE2_4 (0x10UL << DCMI_DR_BYTE2_Pos) /*!< 0x00100000 */
6933 #define DCMI_DR_BYTE2_5 (0x20UL << DCMI_DR_BYTE2_Pos) /*!< 0x00200000 */
6934 #define DCMI_DR_BYTE2_6 (0x40UL << DCMI_DR_BYTE2_Pos) /*!< 0x00400000 */
6935 #define DCMI_DR_BYTE2_7 (0x80UL << DCMI_DR_BYTE2_Pos) /*!< 0x00800000 */
Dstm32l4s5xx.h7091 #define DCMI_DR_BYTE2_Pos (16U) macro
7092 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
7094 #define DCMI_DR_BYTE2_0 (0x01UL << DCMI_DR_BYTE2_Pos) /*!< 0x00010000 */
7095 #define DCMI_DR_BYTE2_1 (0x02UL << DCMI_DR_BYTE2_Pos) /*!< 0x00020000 */
7096 #define DCMI_DR_BYTE2_2 (0x04UL << DCMI_DR_BYTE2_Pos) /*!< 0x00040000 */
7097 #define DCMI_DR_BYTE2_3 (0x08UL << DCMI_DR_BYTE2_Pos) /*!< 0x00080000 */
7098 #define DCMI_DR_BYTE2_4 (0x10UL << DCMI_DR_BYTE2_Pos) /*!< 0x00100000 */
7099 #define DCMI_DR_BYTE2_5 (0x20UL << DCMI_DR_BYTE2_Pos) /*!< 0x00200000 */
7100 #define DCMI_DR_BYTE2_6 (0x40UL << DCMI_DR_BYTE2_Pos) /*!< 0x00400000 */
7101 #define DCMI_DR_BYTE2_7 (0x80UL << DCMI_DR_BYTE2_Pos) /*!< 0x00800000 */
Dstm32l4s7xx.h7177 #define DCMI_DR_BYTE2_Pos (16U) macro
7178 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
7180 #define DCMI_DR_BYTE2_0 (0x01UL << DCMI_DR_BYTE2_Pos) /*!< 0x00010000 */
7181 #define DCMI_DR_BYTE2_1 (0x02UL << DCMI_DR_BYTE2_Pos) /*!< 0x00020000 */
7182 #define DCMI_DR_BYTE2_2 (0x04UL << DCMI_DR_BYTE2_Pos) /*!< 0x00040000 */
7183 #define DCMI_DR_BYTE2_3 (0x08UL << DCMI_DR_BYTE2_Pos) /*!< 0x00080000 */
7184 #define DCMI_DR_BYTE2_4 (0x10UL << DCMI_DR_BYTE2_Pos) /*!< 0x00100000 */
7185 #define DCMI_DR_BYTE2_5 (0x20UL << DCMI_DR_BYTE2_Pos) /*!< 0x00200000 */
7186 #define DCMI_DR_BYTE2_6 (0x40UL << DCMI_DR_BYTE2_Pos) /*!< 0x00400000 */
7187 #define DCMI_DR_BYTE2_7 (0x80UL << DCMI_DR_BYTE2_Pos) /*!< 0x00800000 */
Dstm32l4p5xx.h7121 #define DCMI_DR_BYTE2_Pos (16U) macro
7122 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
7124 #define DCMI_DR_BYTE2_0 (0x01UL << DCMI_DR_BYTE2_Pos) /*!< 0x00010000 */
7125 #define DCMI_DR_BYTE2_1 (0x02UL << DCMI_DR_BYTE2_Pos) /*!< 0x00020000 */
7126 #define DCMI_DR_BYTE2_2 (0x04UL << DCMI_DR_BYTE2_Pos) /*!< 0x00040000 */
7127 #define DCMI_DR_BYTE2_3 (0x08UL << DCMI_DR_BYTE2_Pos) /*!< 0x00080000 */
7128 #define DCMI_DR_BYTE2_4 (0x10UL << DCMI_DR_BYTE2_Pos) /*!< 0x00100000 */
7129 #define DCMI_DR_BYTE2_5 (0x20UL << DCMI_DR_BYTE2_Pos) /*!< 0x00200000 */
7130 #define DCMI_DR_BYTE2_6 (0x40UL << DCMI_DR_BYTE2_Pos) /*!< 0x00400000 */
7131 #define DCMI_DR_BYTE2_7 (0x80UL << DCMI_DR_BYTE2_Pos) /*!< 0x00800000 */
Dstm32l4q5xx.h7361 #define DCMI_DR_BYTE2_Pos (16U) macro
7362 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
7364 #define DCMI_DR_BYTE2_0 (0x01UL << DCMI_DR_BYTE2_Pos) /*!< 0x00010000 */
7365 #define DCMI_DR_BYTE2_1 (0x02UL << DCMI_DR_BYTE2_Pos) /*!< 0x00020000 */
7366 #define DCMI_DR_BYTE2_2 (0x04UL << DCMI_DR_BYTE2_Pos) /*!< 0x00040000 */
7367 #define DCMI_DR_BYTE2_3 (0x08UL << DCMI_DR_BYTE2_Pos) /*!< 0x00080000 */
7368 #define DCMI_DR_BYTE2_4 (0x10UL << DCMI_DR_BYTE2_Pos) /*!< 0x00100000 */
7369 #define DCMI_DR_BYTE2_5 (0x20UL << DCMI_DR_BYTE2_Pos) /*!< 0x00200000 */
7370 #define DCMI_DR_BYTE2_6 (0x40UL << DCMI_DR_BYTE2_Pos) /*!< 0x00400000 */
7371 #define DCMI_DR_BYTE2_7 (0x80UL << DCMI_DR_BYTE2_Pos) /*!< 0x00800000 */
Dstm32l4r9xx.h7007 #define DCMI_DR_BYTE2_Pos (16U) macro
7008 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
7010 #define DCMI_DR_BYTE2_0 (0x01UL << DCMI_DR_BYTE2_Pos) /*!< 0x00010000 */
7011 #define DCMI_DR_BYTE2_1 (0x02UL << DCMI_DR_BYTE2_Pos) /*!< 0x00020000 */
7012 #define DCMI_DR_BYTE2_2 (0x04UL << DCMI_DR_BYTE2_Pos) /*!< 0x00040000 */
7013 #define DCMI_DR_BYTE2_3 (0x08UL << DCMI_DR_BYTE2_Pos) /*!< 0x00080000 */
7014 #define DCMI_DR_BYTE2_4 (0x10UL << DCMI_DR_BYTE2_Pos) /*!< 0x00100000 */
7015 #define DCMI_DR_BYTE2_5 (0x20UL << DCMI_DR_BYTE2_Pos) /*!< 0x00200000 */
7016 #define DCMI_DR_BYTE2_6 (0x40UL << DCMI_DR_BYTE2_Pos) /*!< 0x00400000 */
7017 #define DCMI_DR_BYTE2_7 (0x80UL << DCMI_DR_BYTE2_Pos) /*!< 0x00800000 */
Dstm32l4s9xx.h7259 #define DCMI_DR_BYTE2_Pos (16U) macro
7260 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
7262 #define DCMI_DR_BYTE2_0 (0x01UL << DCMI_DR_BYTE2_Pos) /*!< 0x00010000 */
7263 #define DCMI_DR_BYTE2_1 (0x02UL << DCMI_DR_BYTE2_Pos) /*!< 0x00020000 */
7264 #define DCMI_DR_BYTE2_2 (0x04UL << DCMI_DR_BYTE2_Pos) /*!< 0x00040000 */
7265 #define DCMI_DR_BYTE2_3 (0x08UL << DCMI_DR_BYTE2_Pos) /*!< 0x00080000 */
7266 #define DCMI_DR_BYTE2_4 (0x10UL << DCMI_DR_BYTE2_Pos) /*!< 0x00100000 */
7267 #define DCMI_DR_BYTE2_5 (0x20UL << DCMI_DR_BYTE2_Pos) /*!< 0x00200000 */
7268 #define DCMI_DR_BYTE2_6 (0x40UL << DCMI_DR_BYTE2_Pos) /*!< 0x00400000 */
7269 #define DCMI_DR_BYTE2_7 (0x80UL << DCMI_DR_BYTE2_Pos) /*!< 0x00800000 */
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f207xx.h5799 #define DCMI_DR_BYTE2_Pos (16U) macro
5800 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
Dstm32f217xx.h5949 #define DCMI_DR_BYTE2_Pos (16U) macro
5950 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f407xx.h5798 #define DCMI_DR_BYTE2_Pos (16U) macro
5799 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
Dstm32f427xx.h5889 #define DCMI_DR_BYTE2_Pos (16U) macro
5890 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
Dstm32f446xx.h5966 #define DCMI_DR_BYTE2_Pos (16U) macro
5967 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
Dstm32f417xx.h5977 #define DCMI_DR_BYTE2_Pos (16U) macro
5978 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
Dstm32f429xx.h5948 #define DCMI_DR_BYTE2_Pos (16U) macro
5949 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
Dstm32f439xx.h6135 #define DCMI_DR_BYTE2_Pos (16U) macro
6136 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
Dstm32f437xx.h6081 #define DCMI_DR_BYTE2_Pos (16U) macro
6082 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f750xx.h6230 #define DCMI_DR_BYTE2_Pos (16U) macro
6231 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
Dstm32f745xx.h5987 #define DCMI_DR_BYTE2_Pos (16U) macro
5988 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
Dstm32f756xx.h6230 #define DCMI_DR_BYTE2_Pos (16U) macro
6231 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
Dstm32f746xx.h6042 #define DCMI_DR_BYTE2_Pos (16U) macro
6043 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
Dstm32f765xx.h6442 #define DCMI_DR_BYTE2_Pos (16U) macro
6443 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
Dstm32f777xx.h6724 #define DCMI_DR_BYTE2_Pos (16U) macro
6725 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */

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