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Searched refs:DCMI_DR_BYTE0_Pos (Results 1 – 25 of 97) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l4a6xx.h7130 #define DCMI_DR_BYTE0_Pos (0U) macro
7131 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
7133 #define DCMI_DR_BYTE0_0 (0x01UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000001 */
7134 #define DCMI_DR_BYTE0_1 (0x02UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000002 */
7135 #define DCMI_DR_BYTE0_2 (0x04UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000004 */
7136 #define DCMI_DR_BYTE0_3 (0x08UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000008 */
7137 #define DCMI_DR_BYTE0_4 (0x10UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000010 */
7138 #define DCMI_DR_BYTE0_5 (0x20UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000020 */
7139 #define DCMI_DR_BYTE0_6 (0x40UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000040 */
7140 #define DCMI_DR_BYTE0_7 (0x80UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000080 */
Dstm32l496xx.h6885 #define DCMI_DR_BYTE0_Pos (0U) macro
6886 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
6888 #define DCMI_DR_BYTE0_0 (0x01UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000001 */
6889 #define DCMI_DR_BYTE0_1 (0x02UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000002 */
6890 #define DCMI_DR_BYTE0_2 (0x04UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000004 */
6891 #define DCMI_DR_BYTE0_3 (0x08UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000008 */
6892 #define DCMI_DR_BYTE0_4 (0x10UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000010 */
6893 #define DCMI_DR_BYTE0_5 (0x20UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000020 */
6894 #define DCMI_DR_BYTE0_6 (0x40UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000040 */
6895 #define DCMI_DR_BYTE0_7 (0x80UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000080 */
Dstm32l4r5xx.h6817 #define DCMI_DR_BYTE0_Pos (0U) macro
6818 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
6820 #define DCMI_DR_BYTE0_0 (0x01UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000001 */
6821 #define DCMI_DR_BYTE0_1 (0x02UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000002 */
6822 #define DCMI_DR_BYTE0_2 (0x04UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000004 */
6823 #define DCMI_DR_BYTE0_3 (0x08UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000008 */
6824 #define DCMI_DR_BYTE0_4 (0x10UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000010 */
6825 #define DCMI_DR_BYTE0_5 (0x20UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000020 */
6826 #define DCMI_DR_BYTE0_6 (0x40UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000040 */
6827 #define DCMI_DR_BYTE0_7 (0x80UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000080 */
Dstm32l4r7xx.h6903 #define DCMI_DR_BYTE0_Pos (0U) macro
6904 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
6906 #define DCMI_DR_BYTE0_0 (0x01UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000001 */
6907 #define DCMI_DR_BYTE0_1 (0x02UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000002 */
6908 #define DCMI_DR_BYTE0_2 (0x04UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000004 */
6909 #define DCMI_DR_BYTE0_3 (0x08UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000008 */
6910 #define DCMI_DR_BYTE0_4 (0x10UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000010 */
6911 #define DCMI_DR_BYTE0_5 (0x20UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000020 */
6912 #define DCMI_DR_BYTE0_6 (0x40UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000040 */
6913 #define DCMI_DR_BYTE0_7 (0x80UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000080 */
Dstm32l4s5xx.h7069 #define DCMI_DR_BYTE0_Pos (0U) macro
7070 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
7072 #define DCMI_DR_BYTE0_0 (0x01UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000001 */
7073 #define DCMI_DR_BYTE0_1 (0x02UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000002 */
7074 #define DCMI_DR_BYTE0_2 (0x04UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000004 */
7075 #define DCMI_DR_BYTE0_3 (0x08UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000008 */
7076 #define DCMI_DR_BYTE0_4 (0x10UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000010 */
7077 #define DCMI_DR_BYTE0_5 (0x20UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000020 */
7078 #define DCMI_DR_BYTE0_6 (0x40UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000040 */
7079 #define DCMI_DR_BYTE0_7 (0x80UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000080 */
Dstm32l4s7xx.h7155 #define DCMI_DR_BYTE0_Pos (0U) macro
7156 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
7158 #define DCMI_DR_BYTE0_0 (0x01UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000001 */
7159 #define DCMI_DR_BYTE0_1 (0x02UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000002 */
7160 #define DCMI_DR_BYTE0_2 (0x04UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000004 */
7161 #define DCMI_DR_BYTE0_3 (0x08UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000008 */
7162 #define DCMI_DR_BYTE0_4 (0x10UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000010 */
7163 #define DCMI_DR_BYTE0_5 (0x20UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000020 */
7164 #define DCMI_DR_BYTE0_6 (0x40UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000040 */
7165 #define DCMI_DR_BYTE0_7 (0x80UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000080 */
Dstm32l4p5xx.h7099 #define DCMI_DR_BYTE0_Pos (0U) macro
7100 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
7102 #define DCMI_DR_BYTE0_0 (0x01UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000001 */
7103 #define DCMI_DR_BYTE0_1 (0x02UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000002 */
7104 #define DCMI_DR_BYTE0_2 (0x04UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000004 */
7105 #define DCMI_DR_BYTE0_3 (0x08UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000008 */
7106 #define DCMI_DR_BYTE0_4 (0x10UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000010 */
7107 #define DCMI_DR_BYTE0_5 (0x20UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000020 */
7108 #define DCMI_DR_BYTE0_6 (0x40UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000040 */
7109 #define DCMI_DR_BYTE0_7 (0x80UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000080 */
Dstm32l4q5xx.h7339 #define DCMI_DR_BYTE0_Pos (0U) macro
7340 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
7342 #define DCMI_DR_BYTE0_0 (0x01UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000001 */
7343 #define DCMI_DR_BYTE0_1 (0x02UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000002 */
7344 #define DCMI_DR_BYTE0_2 (0x04UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000004 */
7345 #define DCMI_DR_BYTE0_3 (0x08UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000008 */
7346 #define DCMI_DR_BYTE0_4 (0x10UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000010 */
7347 #define DCMI_DR_BYTE0_5 (0x20UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000020 */
7348 #define DCMI_DR_BYTE0_6 (0x40UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000040 */
7349 #define DCMI_DR_BYTE0_7 (0x80UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000080 */
Dstm32l4r9xx.h6985 #define DCMI_DR_BYTE0_Pos (0U) macro
6986 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
6988 #define DCMI_DR_BYTE0_0 (0x01UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000001 */
6989 #define DCMI_DR_BYTE0_1 (0x02UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000002 */
6990 #define DCMI_DR_BYTE0_2 (0x04UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000004 */
6991 #define DCMI_DR_BYTE0_3 (0x08UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000008 */
6992 #define DCMI_DR_BYTE0_4 (0x10UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000010 */
6993 #define DCMI_DR_BYTE0_5 (0x20UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000020 */
6994 #define DCMI_DR_BYTE0_6 (0x40UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000040 */
6995 #define DCMI_DR_BYTE0_7 (0x80UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000080 */
Dstm32l4s9xx.h7237 #define DCMI_DR_BYTE0_Pos (0U) macro
7238 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
7240 #define DCMI_DR_BYTE0_0 (0x01UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000001 */
7241 #define DCMI_DR_BYTE0_1 (0x02UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000002 */
7242 #define DCMI_DR_BYTE0_2 (0x04UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000004 */
7243 #define DCMI_DR_BYTE0_3 (0x08UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000008 */
7244 #define DCMI_DR_BYTE0_4 (0x10UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000010 */
7245 #define DCMI_DR_BYTE0_5 (0x20UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000020 */
7246 #define DCMI_DR_BYTE0_6 (0x40UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000040 */
7247 #define DCMI_DR_BYTE0_7 (0x80UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000080 */
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f207xx.h5793 #define DCMI_DR_BYTE0_Pos (0U) macro
5794 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
Dstm32f217xx.h5943 #define DCMI_DR_BYTE0_Pos (0U) macro
5944 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f407xx.h5792 #define DCMI_DR_BYTE0_Pos (0U) macro
5793 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
Dstm32f427xx.h5883 #define DCMI_DR_BYTE0_Pos (0U) macro
5884 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
Dstm32f446xx.h5960 #define DCMI_DR_BYTE0_Pos (0U) macro
5961 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
Dstm32f417xx.h5971 #define DCMI_DR_BYTE0_Pos (0U) macro
5972 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
Dstm32f429xx.h5942 #define DCMI_DR_BYTE0_Pos (0U) macro
5943 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
Dstm32f439xx.h6129 #define DCMI_DR_BYTE0_Pos (0U) macro
6130 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
Dstm32f437xx.h6075 #define DCMI_DR_BYTE0_Pos (0U) macro
6076 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f750xx.h6224 #define DCMI_DR_BYTE0_Pos (0U) macro
6225 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
Dstm32f745xx.h5981 #define DCMI_DR_BYTE0_Pos (0U) macro
5982 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
Dstm32f756xx.h6224 #define DCMI_DR_BYTE0_Pos (0U) macro
6225 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
Dstm32f746xx.h6036 #define DCMI_DR_BYTE0_Pos (0U) macro
6037 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
Dstm32f765xx.h6436 #define DCMI_DR_BYTE0_Pos (0U) macro
6437 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
Dstm32f777xx.h6718 #define DCMI_DR_BYTE0_Pos (0U) macro
6719 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */

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