Searched refs:DCMIPP_P0DCLMTR_ENABLE_Pos (Results 1 – 8 of 8) sorted by relevance
4543 #define DCMIPP_P0DCLMTR_ENABLE_Pos (31U) macro4544 #define DCMIPP_P0DCLMTR_ENABLE_Msk (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos) /*!< 0x80000000 */
5067 #define DCMIPP_P0DCLMTR_ENABLE_Pos (31U) macro5068 #define DCMIPP_P0DCLMTR_ENABLE_Msk (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos) /*!< 0x80000000 */
4988 #define DCMIPP_P0DCLMTR_ENABLE_Pos (31U) macro4989 #define DCMIPP_P0DCLMTR_ENABLE_Msk (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos) /*!< 0x80000000 */
4620 #define DCMIPP_P0DCLMTR_ENABLE_Pos (31U) macro4621 #define DCMIPP_P0DCLMTR_ENABLE_Msk (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos) /*!< 0x80000000 */
9093 #define DCMIPP_P0DCLMTR_ENABLE_Pos (31U) macro9094 #define DCMIPP_P0DCLMTR_ENABLE_Msk (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos) /*!< 0…
10035 #define DCMIPP_P0DCLMTR_ENABLE_Pos (31U) macro10036 #define DCMIPP_P0DCLMTR_ENABLE_Msk (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos) /*!< 0…
9793 #define DCMIPP_P0DCLMTR_ENABLE_Pos (31U) macro9794 #define DCMIPP_P0DCLMTR_ENABLE_Msk (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos) /*!< 0…
9335 #define DCMIPP_P0DCLMTR_ENABLE_Pos (31U) macro9336 #define DCMIPP_P0DCLMTR_ENABLE_Msk (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos) /*!< 0…