Searched refs:DCMIPP_P0CSCSZR_ENABLE_Pos (Results 1 – 8 of 8) sorted by relevance
4666 #define DCMIPP_P0CSCSZR_ENABLE_Pos (31U) macro4667 #define DCMIPP_P0CSCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos) /*!< 0x80000000 */
5190 #define DCMIPP_P0CSCSZR_ENABLE_Pos (31U) macro5191 #define DCMIPP_P0CSCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos) /*!< 0x80000000 */
5111 #define DCMIPP_P0CSCSZR_ENABLE_Pos (31U) macro5112 #define DCMIPP_P0CSCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos) /*!< 0x80000000 */
4743 #define DCMIPP_P0CSCSZR_ENABLE_Pos (31U) macro4744 #define DCMIPP_P0CSCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos) /*!< 0x80000000 */
9242 #define DCMIPP_P0CSCSZR_ENABLE_Pos (31U) macro9243 #define DCMIPP_P0CSCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos) /*!< 0…
10184 #define DCMIPP_P0CSCSZR_ENABLE_Pos (31U) macro10185 #define DCMIPP_P0CSCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos) /*!< 0…
9942 #define DCMIPP_P0CSCSZR_ENABLE_Pos (31U) macro9943 #define DCMIPP_P0CSCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos) /*!< 0…
9484 #define DCMIPP_P0CSCSZR_ENABLE_Pos (31U) macro9485 #define DCMIPP_P0CSCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos) /*!< 0…