Searched refs:DCMIPP_CMSR1_PRVSYNC_Pos (Results 1 – 8 of 8) sorted by relevance
4443 #define DCMIPP_CMSR1_PRVSYNC_Pos (1U) macro4444 #define DCMIPP_CMSR1_PRVSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos) /*!< 0x00000002 */
4967 #define DCMIPP_CMSR1_PRVSYNC_Pos (1U) macro4968 #define DCMIPP_CMSR1_PRVSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos) /*!< 0x00000002 */
4888 #define DCMIPP_CMSR1_PRVSYNC_Pos (1U) macro4889 #define DCMIPP_CMSR1_PRVSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos) /*!< 0x00000002 */
4520 #define DCMIPP_CMSR1_PRVSYNC_Pos (1U) macro4521 #define DCMIPP_CMSR1_PRVSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos) /*!< 0x00000002 */
8909 #define DCMIPP_CMSR1_PRVSYNC_Pos (1U) macro8910 #define DCMIPP_CMSR1_PRVSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos) /*!< 0…
9851 #define DCMIPP_CMSR1_PRVSYNC_Pos (1U) macro9852 #define DCMIPP_CMSR1_PRVSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos) /*!< 0…
9609 #define DCMIPP_CMSR1_PRVSYNC_Pos (1U) macro9610 #define DCMIPP_CMSR1_PRVSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos) /*!< 0…
9151 #define DCMIPP_CMSR1_PRVSYNC_Pos (1U) macro9152 #define DCMIPP_CMSR1_PRVSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos) /*!< 0…