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Searched refs:D3CR (Results 1 – 19 of 19) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_pwr.h266 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \
268 tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
281 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
283 tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
292 MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
294 tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
382 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\
407 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\
424 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\
Dstm32h7xx_ll_pwr.h1578 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); in LL_PWR_SetRegulVoltageScaling()
1598 return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS)); in LL_PWR_GetRegulVoltageScaling()
2111 return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VOS()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_pwr_ex.c441 MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); in HAL_PWREx_ControlVoltageScaling()
488 MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); in HAL_PWREx_ControlVoltageScaling()
492 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); in HAL_PWREx_ControlVoltageScaling()
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h730xxq.h1225 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ member
Dstm32h733xx.h1224 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ member
Dstm32h725xx.h1222 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ member
Dstm32h730xx.h1224 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ member
Dstm32h735xx.h1225 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ member
Dstm32h742xx.h1131 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ member
Dstm32h723xx.h1221 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ member
Dstm32h750xx.h1219 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ member
Dstm32h753xx.h1219 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ member
Dstm32h745xx.h1264 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ member
Dstm32h745xg.h1264 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ member
Dstm32h743xx.h1218 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ member
Dstm32h755xx.h1265 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ member
Dstm32h757xx.h1346 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ member
Dstm32h747xg.h1345 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ member
Dstm32h747xx.h1345 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ member