Home
last modified time | relevance | path

Searched refs:CTR3 (Results 1 – 25 of 42) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h4473 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, in LL_DMA_ConfigAddrUpdateValue()
4491 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR… in LL_DMA_SetDestAddrUpdateValue()
4508 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, in LL_DMA_GetDestAddrUpdateValue()
4526 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR… in LL_DMA_SetSrcAddrUpdateValue()
4543 …return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, D… in LL_DMA_GetSrcAddrUpdateValue()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h4535 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, in LL_DMA_ConfigAddrUpdateValue()
4555 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR… in LL_DMA_SetDestAddrUpdateValue()
4574 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, in LL_DMA_GetDestAddrUpdateValue()
4594 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR… in LL_DMA_SetSrcAddrUpdateValue()
4613 …return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, D… in LL_DMA_GetSrcAddrUpdateValue()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_dma.h4355 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, in LL_DMA_ConfigAddrUpdateValue()
4375 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR… in LL_DMA_SetDestAddrUpdateValue()
4394 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, in LL_DMA_GetDestAddrUpdateValue()
4414 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR… in LL_DMA_SetSrcAddrUpdateValue()
4433 …return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, D… in LL_DMA_GetSrcAddrUpdateValue()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_dma.c502 hdma->Instance->CTR3 = 0U; in HAL_DMA_DeInit()
1724 WRITE_REG(hdma->Instance->CTR3, 0U); in DMA_Init()
Dstm32h7rsxx_hal_dma_ex.c723 hdma->Instance->CTR3 = 0U; in HAL_DMAEx_List_DeInit()
3374 WRITE_REG(hdma->Instance->CTR3, tmpreg2); in HAL_DMAEx_ConfigRepeatBlock()
3672 WRITE_REG(hdma->Instance->CTR3, 0U); in DMA_List_Init()
Dstm32h7rsxx_ll_dma.c375 LL_DMA_WriteReg(tmp, CTR3, 0U); in LL_DMA_DeInit()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_dma.h5673 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, in LL_DMA_ConfigAddrUpdateValue()
5693 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR… in LL_DMA_SetDestAddrUpdateValue()
5712 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, in LL_DMA_GetDestAddrUpdateValue()
5732 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR… in LL_DMA_SetSrcAddrUpdateValue()
5751 …return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, D… in LL_DMA_GetSrcAddrUpdateValue()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_dma.c377 hdma->Instance->CTR3 = 0U; in HAL_DMA_DeInit()
1678 WRITE_REG(hdma->Instance->CTR3, 0U); in DMA_Init()
Dstm32h5xx_hal_dma_ex.c727 hdma->Instance->CTR3 = 0U; in HAL_DMAEx_List_DeInit()
3390 WRITE_REG(hdma->Instance->CTR3, tmpreg2); in HAL_DMAEx_ConfigRepeatBlock()
3688 WRITE_REG(hdma->Instance->CTR3, 0U); in DMA_List_Init()
Dstm32h5xx_ll_dma.c340 LL_DMA_WriteReg(tmp, CTR3, 0U); in LL_DMA_DeInit()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_dma.c420 hdma->Instance->CTR3 = 0U; in HAL_DMA_DeInit()
1782 WRITE_REG(hdma->Instance->CTR3, 0U); in DMA_Init()
Dstm32n6xx_hal_dma_ex.c731 hdma->Instance->CTR3 = 0U; in HAL_DMAEx_List_DeInit()
3410 WRITE_REG(hdma->Instance->CTR3, tmpreg2); in HAL_DMAEx_ConfigRepeatBlock()
3708 WRITE_REG(hdma->Instance->CTR3, 0U); in DMA_List_Init()
Dstm32n6xx_ll_dma.c392 LL_DMA_WriteReg(tmp, CTR3, 0U); in LL_DMA_DeInit()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_dma.c370 hdma->Instance->CTR3 = 0U; in HAL_DMA_DeInit()
1659 WRITE_REG(hdma->Instance->CTR3, 0U); in DMA_Init()
Dstm32u5xx_hal_dma_ex.c727 hdma->Instance->CTR3 = 0U; in HAL_DMAEx_List_DeInit()
3391 WRITE_REG(hdma->Instance->CTR3, tmpreg2); in HAL_DMAEx_ConfigRepeatBlock()
3689 WRITE_REG(hdma->Instance->CTR3, 0U); in DMA_List_Init()
Dstm32u5xx_ll_dma.c343 LL_DMA_WriteReg(tmp, CTR3, 0U); in LL_DMA_DeInit()
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h414 …__IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: … member
Dstm32h523xx.h475 …__IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: … member
Dstm32h562xx.h495 …__IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: … member
Dstm32h533xx.h512 …__IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: … member
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h443 …__IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: … member
Dstm32u535xx.h404 …__IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: … member
Dstm32u575xx.h415 …__IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: … member
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h548 …__IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset:… member
Dstm32h7s7xx.h603 …__IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset:… member

12