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Searched refs:COMP_CSR_COMP1INNSEL_Pos (Results 1 – 15 of 15) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h1026 #define COMP_CSR_COMP1INNSEL_Pos (4U) macro
1027 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
1029 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
1030 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
Dstm32l011xx.h889 #define COMP_CSR_COMP1INNSEL_Pos (4U) macro
890 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
892 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
893 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
Dstm32l021xx.h1017 #define COMP_CSR_COMP1INNSEL_Pos (4U) macro
1018 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
1020 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
1021 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
Dstm32l031xx.h898 #define COMP_CSR_COMP1INNSEL_Pos (4U) macro
899 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
901 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
902 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
Dstm32l051xx.h933 #define COMP_CSR_COMP1INNSEL_Pos (4U) macro
934 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
936 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
937 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
Dstm32l081xx.h1083 #define COMP_CSR_COMP1INNSEL_Pos (4U) macro
1084 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
1086 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
1087 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
Dstm32l071xx.h955 #define COMP_CSR_COMP1INNSEL_Pos (4U) macro
956 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
958 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
959 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
Dstm32l052xx.h1042 #define COMP_CSR_COMP1INNSEL_Pos (4U) macro
1043 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
1045 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
1046 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
Dstm32l062xx.h1170 #define COMP_CSR_COMP1INNSEL_Pos (4U) macro
1171 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
1173 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
1174 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
Dstm32l053xx.h1064 #define COMP_CSR_COMP1INNSEL_Pos (4U) macro
1065 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
1067 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
1068 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
Dstm32l072xx.h1069 #define COMP_CSR_COMP1INNSEL_Pos (4U) macro
1070 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
1072 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
1073 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
Dstm32l073xx.h1091 #define COMP_CSR_COMP1INNSEL_Pos (4U) macro
1092 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
1094 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
1095 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
Dstm32l083xx.h1219 #define COMP_CSR_COMP1INNSEL_Pos (4U) macro
1220 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
1222 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
1223 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
Dstm32l063xx.h1192 #define COMP_CSR_COMP1INNSEL_Pos (4U) macro
1193 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
1195 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
1196 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
Dstm32l082xx.h1197 #define COMP_CSR_COMP1INNSEL_Pos (4U) macro
1198 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
1200 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
1201 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */