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Searched refs:CM0AR (Results 1 – 25 of 32) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_dma_ex.c296 hdma->Instance->CM0AR = Address; in HAL_DMAEx_ChangeMemory()
532 hdma->Instance->CM0AR = SrcAddress; in DMA_MultiBufferSetConfig()
541 hdma->Instance->CM0AR = DstAddress; in DMA_MultiBufferSetConfig()
Dstm32l5xx_hal_dma.c1294 hdma->Instance->CM0AR = SrcAddress; in DMA_SetConfig()
1303 hdma->Instance->CM0AR = DstAddress; in DMA_SetConfig()
Dstm32l5xx_ll_dma.c182 WRITE_REG(tmp->CM0AR, 0U); in LL_DMA_DeInit()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_bdma.h1165 …WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, SrcA… in LL_BDMA_ConfigAddresses()
1172 …WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, DstA… in LL_BDMA_ConfigAddresses()
1198 …WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, Memo… in LL_BDMA_SetMemoryAddress()
1246 …urn (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR)); in LL_BDMA_GetMemoryAddress()
1319 …WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, Memo… in LL_BDMA_SetM2MDstAddress()
1365 …urn (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR)); in LL_BDMA_GetM2MDstAddress()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_dma.h1466 …WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM0AR, SrcAddres… in LL_DMA_ConfigAddresses()
1473 …WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM0AR, DstAddres… in LL_DMA_ConfigAddresses()
1498 …WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM0AR, MemoryAdd… in LL_DMA_SetMemoryAddress()
1544 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM0AR)); in LL_DMA_GetMemoryAddress()
1614 …WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM0AR, MemoryAdd… in LL_DMA_SetM2MDstAddress()
1658 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM0AR)); in LL_DMA_GetM2MDstAddress()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_dma_ex.c377 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = Address; in HAL_DMAEx_ChangeMemory()
686 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; in DMA_MultiBufferSetConfig()
695 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; in DMA_MultiBufferSetConfig()
Dstm32h7xx_hal_dma.c520 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = 0U; in HAL_DMA_DeInit()
1836 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; in DMA_SetConfig()
1845 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; in DMA_SetConfig()
Dstm32h7xx_ll_bdma.c169 LL_BDMA_WriteReg(tmp, CM0AR, 0U); in LL_BDMA_DeInit()
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h475 …__IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register, Address offset: 0x1… member
Dstm32l562xx.h509 …__IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register, Address offset: 0x1… member
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h600 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ member
Dstm32h7b0xx.h603 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ member
Dstm32h7b0xxq.h604 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ member
Dstm32h7a3xxq.h601 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ member
Dstm32h7b3xx.h603 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ member
Dstm32h7b3xxq.h604 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ member
Dstm32h730xxq.h627 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ member
Dstm32h733xx.h626 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ member
Dstm32h725xx.h624 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ member
Dstm32h730xx.h626 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ member
Dstm32h735xx.h627 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ member
Dstm32h742xx.h579 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ member
Dstm32h723xx.h623 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ member
Dstm32h750xx.h583 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ member
Dstm32h753xx.h583 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ member

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