1 /* USER CODE BEGIN Header */ 2 /** 3 ****************************************************************************** 4 * @file app_conf.h 5 * @author MCD Application Team 6 * @brief Application configuration file for STM32WPAN Middleware. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2020-2021 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 /* USER CODE END Header */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef APP_CONF_H 23 #define APP_CONF_H 24 25 #include "hw.h" 26 /* Z-WB-1: hw_conf.h file is not used, remove the dependency */ 27 /* #include "hw_conf.h" */ 28 #include "hw_if.h" 29 #include "ble_bufsize.h" 30 31 /****************************************************************************** 32 * Application Config 33 ******************************************************************************/ 34 35 /**< generic parameters ******************************************************/ 36 37 /** 38 * Define Tx Power 39 */ 40 #define CFG_TX_POWER (0x18) /* -0.15dBm */ 41 42 /** 43 * Define Advertising parameters 44 */ 45 #define CFG_ADV_BD_ADDRESS (0x7257acd87a6c) 46 47 /* BD_ADDR type: define proper address. Can only be GAP_PUBLIC_ADDR (0x00) or GAP_STATIC_RANDOM_ADDR (0x01) */ 48 #define CFG_IDENTITY_ADDRESS GAP_PUBLIC_ADDR /* GAP_STATIC_RANDOM_ADDR */ 49 //#define CFG_STATIC_RANDOM_ADDRESS (0x1234567890ab) /**< Static Random Address fixed for lifetime of the device */ 50 51 /* Define privacy: PRIVACY_DISABLED or PRIVACY_ENABLED */ 52 #define CFG_PRIVACY PRIVACY_DISABLED /* PRIVACY_ENABLED */ 53 54 /* if CFG_PRIVACY equals PRIVACY_DISABLED, CFG_BLE_ADDRESS_TYPE has 2 allowed values: GAP_PUBLIC_ADDR or GAP_STATIC_RANDOM_ADDR */ 55 #define CFG_BLE_ADDRESS_TYPE CFG_IDENTITY_ADDRESS /**< Bluetooth address types defined in ble_legacy.h */ 56 57 /* if CFG_PRIVACY equals PRIVACY_ENABLED, CFG_BLE_ADDRESS_TYPE has 2 allowed values: GAP_RESOLVABLE_PRIVATE_ADDR or GAP_NON_RESOLVABLE_PRIVATE_ADDR */ 58 //#define CFG_BLE_ADDRESS_TYPE GAP_RESOLVABLE_PRIVATE_ADDR /* GAP_NON_RESOLVABLE_PRIVATE_ADDR */ 59 60 #define CFG_FAST_CONN_ADV_INTERVAL_MIN (0x80) /**< 80ms */ 61 #define CFG_FAST_CONN_ADV_INTERVAL_MAX (0xA0) /**< 100ms */ 62 #define CFG_LP_CONN_ADV_INTERVAL_MIN (0x640) /**< 1s */ 63 #define CFG_LP_CONN_ADV_INTERVAL_MAX (0xFA0) /**< 2.5s */ 64 65 /** 66 * Define IO Authentication 67 */ 68 #define CFG_BONDING_MODE (1) 69 #define CFG_FIXED_PIN (111111) 70 #define CFG_USED_FIXED_PIN (0) 71 #define CFG_ENCRYPTION_KEY_SIZE_MAX (16) 72 #define CFG_ENCRYPTION_KEY_SIZE_MIN (8) 73 74 /** 75 * Define IO capabilities 76 */ 77 #define CFG_IO_CAPABILITY_DISPLAY_ONLY (0x00) 78 #define CFG_IO_CAPABILITY_DISPLAY_YES_NO (0x01) 79 #define CFG_IO_CAPABILITY_KEYBOARD_ONLY (0x02) 80 #define CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT (0x03) 81 #define CFG_IO_CAPABILITY_KEYBOARD_DISPLAY (0x04) 82 83 #define CFG_IO_CAPABILITY CFG_IO_CAPABILITY_DISPLAY_ONLY 84 85 /** 86 * Define MITM modes 87 */ 88 #define CFG_MITM_PROTECTION_NOT_REQUIRED (0x00) 89 #define CFG_MITM_PROTECTION_REQUIRED (0x01) 90 91 #define CFG_MITM_PROTECTION CFG_MITM_PROTECTION_REQUIRED 92 93 /** 94 * Define Secure Connections Support 95 */ 96 #define CFG_SECURE_NOT_SUPPORTED (0x00) 97 #define CFG_SECURE_OPTIONAL (0x01) 98 #define CFG_SECURE_MANDATORY (0x02) 99 100 #define CFG_SC_SUPPORT CFG_SECURE_NOT_SUPPORTED 101 102 /** 103 * Define Keypress Notification Support 104 */ 105 #define CFG_KEYPRESS_NOT_SUPPORTED (0x00) 106 #define CFG_KEYPRESS_SUPPORTED (0x01) 107 108 #define CFG_KEYPRESS_NOTIFICATION_SUPPORT CFG_KEYPRESS_NOT_SUPPORTED 109 110 /** 111 * Numeric Comparison Answers 112 */ 113 #define YES (0x01) 114 #define NO (0x00) 115 116 /** 117 * Define PHY 118 */ 119 #define ALL_PHYS_PREFERENCE 0x00 120 #define RX_2M_PREFERRED 0x02 121 #define TX_2M_PREFERRED 0x02 122 #define TX_1M 0x01 123 #define TX_2M 0x02 124 #define RX_1M 0x01 125 #define RX_2M 0x02 126 127 /** 128 * Generic Access Appearance 129 */ 130 #define CFG_UNKNOWN_APPEARANCE (0) 131 #define CFG_GAP_APPEARANCE (832) 132 #define BLE_APPEARANCE_HID_MOUSE (962) 133 134 /** 135 * Identity root key used to derive IRK and DHK(Legacy) 136 */ 137 #define CFG_BLE_IR {0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0, 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0} 138 139 /** 140 * Encryption root key used to derive LTK(Legacy) and CSRK 141 */ 142 #define CFG_BLE_ER {0xFE, 0xDC, 0xBA, 0x09, 0x87, 0x65, 0x43, 0x21, 0xFE, 0xDC, 0xBA, 0x09, 0x87, 0x65, 0x43, 0x21} 143 144 /** 145 * SMPS supply 146 * SMPS not used when Set to 0 147 * SMPS used when Set to 1 148 */ 149 #define CFG_USE_SMPS 0 150 151 /* USER CODE BEGIN Generic_Parameters */ 152 153 /* USER CODE END Generic_Parameters */ 154 155 /**< specific parameters */ 156 /*****************************************************/ 157 #define CFG_MAX_CONNECTION (8) 158 159 #define CFG_DATA_ROLE_MODE 2 160 161 /****************************************************************************** 162 * BLE Stack 163 ******************************************************************************/ 164 /** 165 * Maximum number of simultaneous connections that the device will support. 166 * Valid values are from 1 to 8 167 */ 168 #define CFG_BLE_NUM_LINK 2 169 170 /** 171 * Maximum number of Services that can be stored in the GATT database. 172 * Note that the GAP and GATT services are automatically added so this parameter should be 2 plus the number of user services 173 */ 174 #define CFG_BLE_NUM_GATT_SERVICES 8 175 176 /** 177 * Maximum number of Attributes 178 * (i.e. the number of characteristic + the number of characteristic values + the number of descriptors, excluding the services) 179 * that can be stored in the GATT database. 180 * Note that certain characteristics and relative descriptors are added automatically during device initialization 181 * so this parameters should be 9 plus the number of user Attributes 182 */ 183 #define CFG_BLE_NUM_GATT_ATTRIBUTES 68 184 185 /** 186 * Maximum supported ATT_MTU size 187 * This parameter is ignored by the CPU2 when CFG_BLE_OPTIONS has SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY flag set 188 */ 189 #define CFG_BLE_MAX_ATT_MTU (156) 190 191 /** 192 * Size of the storage area for Attribute values 193 * This value depends on the number of attributes used by application. In particular the sum of the following quantities (in octets) should be made for each attribute: 194 * - attribute value length 195 * - 5, if UUID is 16 bit; 19, if UUID is 128 bit 196 * - 2, if server configuration descriptor is used 197 * - 2*DTM_NUM_LINK, if client configuration descriptor is used 198 * - 2, if extended properties is used 199 * The total amount of memory needed is the sum of the above quantities for each attribute. 200 * This parameter is ignored by the CPU2 when CFG_BLE_OPTIONS has SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY flag set 201 */ 202 #define CFG_BLE_ATT_VALUE_ARRAY_SIZE (1344) 203 204 /** 205 * Prepare Write List size in terms of number of packet 206 * This parameter is ignored by the CPU2 when CFG_BLE_OPTIONS has SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY flag set 207 */ 208 #define CFG_BLE_PREPARE_WRITE_LIST_SIZE BLE_PREP_WRITE_X_ATT(CFG_BLE_MAX_ATT_MTU) 209 210 /** 211 * Number of allocated memory blocks 212 * This parameter is overwritten by the CPU2 with an hardcoded optimal value when the parameter CFG_BLE_OPTIONS has SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY flag set 213 */ 214 #define CFG_BLE_MBLOCK_COUNT (BLE_MBLOCKS_CALC(CFG_BLE_PREPARE_WRITE_LIST_SIZE, CFG_BLE_MAX_ATT_MTU, CFG_BLE_NUM_LINK)) 215 216 /** 217 * Enable or disable the Extended Packet length feature. Valid values are 0 or 1. 218 */ 219 #define CFG_BLE_DATA_LENGTH_EXTENSION 1 220 221 /** 222 * Sleep clock accuracy in Peripheral mode (ppm value) 223 */ 224 #define CFG_BLE_PERIPHERAL_SCA 500 225 226 /** 227 * Sleep clock accuracy in Central mode 228 * 0 : 251 ppm to 500 ppm 229 * 1 : 151 ppm to 250 ppm 230 * 2 : 101 ppm to 150 ppm 231 * 3 : 76 ppm to 100 ppm 232 * 4 : 51 ppm to 75 ppm 233 * 5 : 31 ppm to 50 ppm 234 * 6 : 21 ppm to 30 ppm 235 * 7 : 0 ppm to 20 ppm 236 */ 237 #define CFG_BLE_CENTRAL_SCA 0 238 239 /** 240 * LsSource 241 * Some information for Low speed clock mapped in bits field 242 * - bit 0: 1: Calibration for the RF system wakeup clock source 0: No calibration for the RF system wakeup clock source 243 * - bit 1: 1: STM32WB5M Module device 0: Other devices as STM32WBxx SOC, STM32WB1M module 244 * - bit 2: 1: HSE/1024 Clock config 0: LSE Clock config 245 */ 246 #if defined(STM32WB5Mxx) 247 #define CFG_BLE_LS_SOURCE (SHCI_C2_BLE_INIT_CFG_BLE_LS_NOCALIB | SHCI_C2_BLE_INIT_CFG_BLE_LS_MOD5MM_DEV | SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_LSE) 248 #else 249 #define CFG_BLE_LS_SOURCE (SHCI_C2_BLE_INIT_CFG_BLE_LS_NOCALIB | SHCI_C2_BLE_INIT_CFG_BLE_LS_OTHER_DEV | SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_LSE) 250 #endif 251 252 /** 253 * Start up time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us) 254 */ 255 #define CFG_BLE_HSE_STARTUP_TIME 0x148 256 257 /** 258 * Maximum duration of the connection event when the device is in Peripheral mode in units of 625/256 us (~2.44 us) 259 */ 260 #define CFG_BLE_MAX_CONN_EVENT_LENGTH (0xFFFFFFFF) 261 262 /** 263 * Viterbi Mode 264 * 1 : enabled 265 * 0 : disabled 266 */ 267 #define CFG_BLE_VITERBI_MODE 1 268 269 /** 270 * BLE stack Options flags to be configured with: 271 * - SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY 272 * - SHCI_C2_BLE_INIT_OPTIONS_LL_HOST 273 * - SHCI_C2_BLE_INIT_OPTIONS_NO_SVC_CHANGE_DESC 274 * - SHCI_C2_BLE_INIT_OPTIONS_WITH_SVC_CHANGE_DESC 275 * - SHCI_C2_BLE_INIT_OPTIONS_DEVICE_NAME_RO 276 * - SHCI_C2_BLE_INIT_OPTIONS_DEVICE_NAME_RW 277 * - SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV 278 * - SHCI_C2_BLE_INIT_OPTIONS_NO_EXT_ADV 279 * - SHCI_C2_BLE_INIT_OPTIONS_CS_ALGO2 280 * - SHCI_C2_BLE_INIT_OPTIONS_NO_CS_ALGO2 281 * - SHCI_C2_BLE_INIT_OPTIONS_REDUC_GATTDB_NVM 282 * - SHCI_C2_BLE_INIT_OPTIONS_FULL_GATTDB_NVM 283 * - SHCI_C2_BLE_INIT_OPTIONS_GATT_CACHING_USED 284 * - SHCI_C2_BLE_INIT_OPTIONS_GATT_CACHING_NOTUSED 285 * - SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_1 286 * - SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_2_3 287 * which are used to set following configuration bits: 288 * (bit 0): 1: LL only 289 * 0: LL + host 290 * (bit 1): 1: no service change desc. 291 * 0: with service change desc. 292 * (bit 2): 1: device name Read-Only 293 * 0: device name R/W 294 * (bit 3): 1: extended advertizing supported 295 * 0: extended advertizing not supported 296 * (bit 4): 1: CS Algo #2 supported 297 * 0: CS Algo #2 not supported 298 * (bit 5): 1: Reduced GATT database in NVM 299 * 0: Full GATT database in NVM 300 * (bit 6): 1: GATT caching is used 301 * 0: GATT caching is not used 302 * (bit 7): 1: LE Power Class 1 303 * 0: LE Power Class 2-3 304 * other bits: complete with Options_extension flag 305 */ 306 /* Z-WB-3 */ 307 #define CFG_BLE_OPTIONS (SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY | SHCI_C2_BLE_INIT_OPTIONS_WITH_SVC_CHANGE_DESC | SHCI_C2_BLE_INIT_OPTIONS_DEVICE_NAME_RW | SHCI_C2_BLE_INIT_OPTIONS_NO_EXT_ADV | SHCI_C2_BLE_INIT_OPTIONS_NO_CS_ALGO2 | SHCI_C2_BLE_INIT_OPTIONS_FULL_GATTDB_NVM | SHCI_C2_BLE_INIT_OPTIONS_GATT_CACHING_NOTUSED | SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_2_3) 308 309 /** 310 * BLE stack Options_extension flags to be configured with: 311 * - SHCI_C2_BLE_INIT_OPTIONS_APPEARANCE_WRITABLE 312 * - SHCI_C2_BLE_INIT_OPTIONS_APPEARANCE_READONLY 313 * - SHCI_C2_BLE_INIT_OPTIONS_ENHANCED_ATT_SUPPORTED 314 * - SHCI_C2_BLE_INIT_OPTIONS_ENHANCED_ATT_NOTSUPPORTED 315 * which are used to set following configuration bits: 316 * (bit 0): 1: appearance Writable 317 * 0: appearance Read-Only 318 * (bit 1): 1: Enhanced ATT supported 319 * 0: Enhanced ATT not supported 320 * other bits: reserved (shall be set to 0) 321 */ 322 #define CFG_BLE_OPTIONS_EXT (SHCI_C2_BLE_INIT_OPTIONS_APPEARANCE_READONLY | SHCI_C2_BLE_INIT_OPTIONS_ENHANCED_ATT_NOTSUPPORTED) 323 324 #define CFG_BLE_MAX_COC_INITIATOR_NBR (32) 325 326 #define CFG_BLE_MIN_TX_POWER (-40) 327 328 #define CFG_BLE_MAX_TX_POWER (6) 329 330 /** 331 * BLE Rx model configuration flags to be configured with: 332 * - SHCI_C2_BLE_INIT_RX_MODEL_AGC_RSSI_LEGACY 333 * - SHCI_C2_BLE_INIT_RX_MODEL_AGC_RSSI_BLOCKER 334 * which are used to set following configuration bits: 335 * (bit 0): 1: agc_rssi model improved vs RF blockers 336 * 0: Legacy agc_rssi model 337 * other bits: reserved (shall be set to 0) 338 */ 339 340 #define CFG_BLE_RX_MODEL_CONFIG (SHCI_C2_BLE_INIT_RX_MODEL_AGC_RSSI_LEGACY) 341 342 /* Maximum number of advertising sets. 343 * Range: 1 .. 8 with limitation: 344 * This parameter is linked to CFG_BLE_MAX_ADV_DATA_LEN such as both compliant with allocated Total memory computed with BLE_EXT_ADV_BUFFER_SIZE based 345 * on Max Extended advertising configuration supported. 346 * This parameter is considered by the CPU2 when CFG_BLE_OPTIONS has SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV flag set 347 */ 348 349 #define CFG_BLE_MAX_ADV_SET_NBR (3) 350 351 /* Maximum advertising data length (in bytes) 352 * Range: 31 .. 1650 with limitation: 353 * This parameter is linked to CFG_BLE_MAX_ADV_SET_NBR such as both compliant with allocated Total memory computed with BLE_EXT_ADV_BUFFER_SIZE based 354 * on Max Extended advertising configuration supported. 355 * This parameter is considered by the CPU2 when CFG_BLE_OPTIONS has SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV flag set 356 */ 357 358 #define CFG_BLE_MAX_ADV_DATA_LEN (1650) 359 360 /* RF TX Path Compensation Value (16-bit signed integer). Units: 0.1 dB. 361 * Range: -1280 .. 1280 362 */ 363 364 #define CFG_BLE_TX_PATH_COMPENS (0) 365 366 /* RF RX Path Compensation Value (16-bit signed integer). Units: 0.1 dB. 367 * Range: -1280 .. 1280 368 */ 369 370 #define CFG_BLE_RX_PATH_COMPENS (0) 371 372 /* BLE core version (16-bit signed integer). 373 * - SHCI_C2_BLE_INIT_BLE_CORE_5_2 374 * - SHCI_C2_BLE_INIT_BLE_CORE_5_3 375 * - SHCI_C2_BLE_INIT_BLE_CORE_5_4 376 * which are used to set: 11(5.2), 12(5.3), 13(5.4). 377 */ 378 379 #define CFG_BLE_CORE_VERSION (SHCI_C2_BLE_INIT_BLE_CORE_5_4) 380 381 382 /****************************************************************************** 383 * Transport Layer 384 ******************************************************************************/ 385 /** 386 * Queue length of BLE Event 387 * This parameter defines the number of asynchronous events that can be stored in the HCI layer before 388 * being reported to the application. When a command is sent to the BLE core coprocessor, the HCI layer 389 * is waiting for the event with the Num_HCI_Command_Packets set to 1. The receive queue shall be large 390 * enough to store all asynchronous events received in between. 391 * When CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE is set to 27, this allow to store three 255 bytes long asynchronous events 392 * between the HCI command and its event. 393 * This parameter depends on the value given to CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE. When the queue size is to small, 394 * the system may hang if the queue is full with asynchronous events and the HCI layer is still waiting 395 * for a CC/CS event, In that case, the notification TL_BLE_HCI_ToNot() is called to indicate 396 * to the application a HCI command did not receive its command event within 30s (Default HCI Timeout). 397 */ 398 #define CFG_TLBLE_EVT_QUEUE_LENGTH 5 399 /** 400 * This parameter should be set to fit most events received by the HCI layer. It defines the buffer size of each element 401 * allocated in the queue of received events and can be used to optimize the amount of RAM allocated by the Memory Manager. 402 * It should not exceed 255 which is the maximum HCI packet payload size (a greater value is a lost of memory as it will 403 * never be used) 404 * It shall be at least 4 to receive the command status event in one frame. 405 * The default value is set to 27 to allow receiving an event of MTU size in a single buffer. This value maybe reduced 406 * further depending on the application. 407 */ 408 #define CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE 255 /**< Set to 255 with the memory manager and the mailbox */ 409 410 #define TL_BLE_EVENT_FRAME_SIZE ( TL_EVT_HDR_SIZE + CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE ) 411 /****************************************************************************** 412 * UART interfaces 413 ******************************************************************************/ 414 415 /** 416 * Select UART interfaces 417 */ 418 #define CFG_UART_GUI 419 #define CFG_DEBUG_TRACE_UART /*hw_uart1*/hw_lpuart1 420 #define CFG_CONSOLE_MENU /*hw_lpuart1*/hw_uart1 421 422 /****************************************************************************** 423 * USB interface 424 ******************************************************************************/ 425 426 /** 427 * Enable/Disable USB interface 428 */ 429 #define CFG_USB_INTERFACE_ENABLE 0 430 431 /****************************************************************************** 432 * IPCC interface 433 ******************************************************************************/ 434 435 /** 436 * The IPCC is dedicated to the communication between the CPU2 and the CPU1 437 * and shall not be modified by the application 438 * The two following definitions shall not be modified 439 */ 440 #define HAL_IPCC_TX_IRQHandler(...) HW_IPCC_Tx_Handler( ) 441 #define HAL_IPCC_RX_IRQHandler(...) HW_IPCC_Rx_Handler( ) 442 443 /****************************************************************************** 444 * Low Power 445 ******************************************************************************/ 446 /** 447 * When set to 1, the low power mode is enable 448 * When set to 0, the device stays in RUN mode 449 */ 450 #define CFG_LPM_SUPPORTED 1 451 452 /****************************************************************************** 453 * RTC interface 454 ******************************************************************************/ 455 #define HAL_RTCEx_WakeUpTimerIRQHandler(...) HW_TS_RTC_Wakeup_Handler( ) 456 457 /****************************************************************************** 458 * Timer Server 459 ******************************************************************************/ 460 /** 461 * CFG_RTC_WUCKSEL_DIVIDER: This sets the RTCCLK divider to the wakeup timer. 462 * The lower is the value, the better is the power consumption and the accuracy of the timerserver 463 * The higher is the value, the finest is the granularity 464 * 465 * CFG_RTC_ASYNCH_PRESCALER: This sets the asynchronous prescaler of the RTC. It should as high as possible ( to output 466 * clock as low as possible) but the output clock should be equal or higher frequency compare to the clock feeding 467 * the wakeup timer. A lower clock speed would impact the accuracy of the timer server. 468 * 469 * CFG_RTC_SYNCH_PRESCALER: This sets the synchronous prescaler of the RTC. 470 * When the 1Hz calendar clock is required, it shall be sets according to other settings 471 * When the 1Hz calendar clock is not needed, CFG_RTC_SYNCH_PRESCALER should be set to 0x7FFF (MAX VALUE) 472 * 473 * CFG_RTCCLK_DIVIDER_CONF: 474 * Shall be set to either 0,2,4,8,16 475 * When set to either 2,4,8,16, the 1Hhz calendar is supported 476 * When set to 0, the user sets its own configuration 477 * 478 * The following settings are computed with LSI as input to the RTC 479 */ 480 481 #define CFG_RTCCLK_DIVIDER_CONF 0 482 483 #if (CFG_RTCCLK_DIVIDER_CONF == 0) 484 /** 485 * Custom configuration 486 * It does not support 1Hz calendar 487 * It divides the RTC CLK by 16 488 */ 489 490 #define CFG_RTCCLK_DIV (16) 491 #define CFG_RTC_WUCKSEL_DIVIDER (0) 492 #define CFG_RTC_ASYNCH_PRESCALER (0x0F) 493 #define CFG_RTC_SYNCH_PRESCALER (0x7FFF) 494 495 #else 496 497 #if (CFG_RTCCLK_DIVIDER_CONF == 2) 498 /** 499 * It divides the RTC CLK by 2 500 */ 501 #define CFG_RTC_WUCKSEL_DIVIDER (3) 502 #endif 503 504 #if (CFG_RTCCLK_DIVIDER_CONF == 4) 505 /** 506 * It divides the RTC CLK by 4 507 */ 508 #define CFG_RTC_WUCKSEL_DIVIDER (2) 509 #endif 510 511 #if (CFG_RTCCLK_DIVIDER_CONF == 8) 512 /** 513 * It divides the RTC CLK by 8 514 */ 515 #define CFG_RTC_WUCKSEL_DIVIDER (1) 516 #endif 517 518 #if (CFG_RTCCLK_DIVIDER_CONF == 16) 519 /** 520 * It divides the RTC CLK by 16 521 */ 522 #define CFG_RTC_WUCKSEL_DIVIDER (0) 523 #endif 524 525 #define CFG_RTCCLK_DIV CFG_RTCCLK_DIVIDER_CONF 526 #define CFG_RTC_ASYNCH_PRESCALER (CFG_RTCCLK_DIV - 1) 527 #define CFG_RTC_SYNCH_PRESCALER (DIVR( LSE_VALUE, (CFG_RTC_ASYNCH_PRESCALER+1) ) - 1 ) 528 529 #endif 530 531 /** tick timer values */ 532 #define CFG_TS_TICK_VAL DIVR( (CFG_RTCCLK_DIV * 1000000), LSE_VALUE ) 533 #define CFG_TS_TICK_VAL_PS DIVR( ((uint64_t)CFG_RTCCLK_DIV * 1e12), (uint64_t)LSE_VALUE ) 534 535 typedef enum 536 { 537 CFG_TIM_PROC_ID_ISR, 538 /* USER CODE BEGIN CFG_TimProcID_t */ 539 540 /* USER CODE END CFG_TimProcID_t */ 541 } CFG_TimProcID_t; 542 543 /****************************************************************************** 544 * Debug 545 ******************************************************************************/ 546 /** 547 * When set, this resets some hw resources to put the device in the same state as at power up. 548 * It resets only register that may prevent the FW to run properly. 549 * 550 * This shall be set to 0 in a final product 551 * 552 */ 553 #define CFG_HW_RESET_BY_FW 1 554 555 /** 556 * keep debugger enabled while in any low power mode when set to 1 557 * should be set to 0 in production 558 */ 559 #define CFG_DEBUGGER_SUPPORTED 1 560 561 /** 562 * When set to 1, the traces are enabled in the BLE services 563 */ 564 #define CFG_DEBUG_BLE_TRACE 1 565 566 /** 567 * Enable or Disable traces in application 568 */ 569 #define CFG_DEBUG_APP_TRACE 1 570 571 #if (CFG_DEBUG_APP_TRACE != 0) 572 #define APP_DBG_MSG PRINT_MESG_DBG 573 #else 574 #define APP_DBG_MSG PRINT_NO_MESG 575 #endif 576 577 #if ( (CFG_DEBUG_BLE_TRACE != 0) || (CFG_DEBUG_APP_TRACE != 0) ) 578 #define CFG_DEBUG_TRACE 1 579 #endif 580 581 #if (CFG_DEBUG_TRACE != 0) 582 #undef CFG_LPM_SUPPORTED 583 #undef CFG_DEBUGGER_SUPPORTED 584 #define CFG_LPM_SUPPORTED 0 585 #define CFG_DEBUGGER_SUPPORTED 1 586 #endif 587 588 /** 589 * When CFG_DEBUG_TRACE_FULL is set to 1, the trace are output with the API name, the file name and the line number 590 * When CFG_DEBUG_TRACE_LIGHT is set to 1, only the debug message is output 591 * 592 * When both are set to 0, no trace are output 593 * When both are set to 1, CFG_DEBUG_TRACE_FULL is selected 594 */ 595 #define CFG_DEBUG_TRACE_LIGHT 1 596 #define CFG_DEBUG_TRACE_FULL 0 597 598 #if (( CFG_DEBUG_TRACE != 0 ) && ( CFG_DEBUG_TRACE_LIGHT == 0 ) && (CFG_DEBUG_TRACE_FULL == 0)) 599 #undef CFG_DEBUG_TRACE_FULL 600 #undef CFG_DEBUG_TRACE_LIGHT 601 #define CFG_DEBUG_TRACE_FULL 0 602 #define CFG_DEBUG_TRACE_LIGHT 1 603 #endif 604 605 #if ( CFG_DEBUG_TRACE == 0 ) 606 #undef CFG_DEBUG_TRACE_FULL 607 #undef CFG_DEBUG_TRACE_LIGHT 608 #define CFG_DEBUG_TRACE_FULL 0 609 #define CFG_DEBUG_TRACE_LIGHT 0 610 #endif 611 612 /** 613 * When not set, the traces is looping on sending the trace over UART 614 */ 615 #define DBG_TRACE_USE_CIRCULAR_QUEUE 1 616 617 /** 618 * max buffer Size to queue data traces and max data trace allowed. 619 * Only Used if DBG_TRACE_USE_CIRCULAR_QUEUE is defined 620 */ 621 #define DBG_TRACE_MSG_QUEUE_SIZE 4096 622 #define MAX_DBG_TRACE_MSG_SIZE 1024 623 624 /* USER CODE BEGIN Defines */ 625 #define CFG_LED_SUPPORTED 1 626 #define CFG_BUTTON_SUPPORTED 1 627 628 #define PUSH_BUTTON_SW1_EXTI_IRQHandler EXTI4_IRQHandler 629 #define PUSH_BUTTON_SW2_EXTI_IRQHandler EXTI0_IRQHandler 630 #define PUSH_BUTTON_SW3_EXTI_IRQHandler EXTI1_IRQHandler 631 /* USER CODE END Defines */ 632 /****************************************************************************** 633 * Scheduler 634 ******************************************************************************/ 635 636 /** 637 * These are the lists of task id registered to the scheduler 638 * Each task id shall be in the range [0:31] 639 * This mechanism allows to implement a generic code in the API TL_BLE_HCI_StatusNot() to comply with 640 * the requirement that a HCI/ACI command shall never be sent if there is already one pending 641 */ 642 643 /**< Add in that list all tasks that may send a ACI/HCI command */ 644 typedef enum 645 { 646 CFG_TASK_CONN_MGR_ID, 647 CFG_TASK_HID_UPDATE_REQ_ID, 648 CFG_TASK_HID_DISC_REQ_ID, 649 CFG_TASK_BAS_LEVEL_REQ_ID, 650 CFG_TASK_HCI_ASYNCH_EVT_ID, 651 652 CFG_LAST_TASK_ID_WITH_HCICMD, /**< Shall be LAST in the list */ 653 } CFG_Task_Id_With_HCI_Cmd_t; 654 655 /**< Add in that list all tasks that never send a ACI/HCI command */ 656 typedef enum 657 { 658 CFG_FIRST_TASK_ID_WITH_NO_HCICMD = CFG_LAST_TASK_ID_WITH_HCICMD - 1, /**< Shall be FIRST in the list */ 659 CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID, 660 /* USER CODE BEGIN CFG_Task_Id_With_NO_HCI_Cmd_t */ 661 662 /* USER CODE END CFG_Task_Id_With_NO_HCI_Cmd_t */ 663 CFG_LAST_TASK_ID_WITH_NO_HCICMD /**< Shall be LAST in the list */ 664 } CFG_Task_Id_With_NO_HCI_Cmd_t; 665 666 #define CFG_TASK_NBR CFG_LAST_TASK_ID_WITH_NO_HCICMD 667 668 /** 669 * This is the list of priority required by the application 670 * Each Id shall be in the range 0..31 671 */ 672 typedef enum 673 { 674 CFG_SCH_PRIO_0, 675 /* USER CODE BEGIN CFG_SCH_Prio_Id_t */ 676 CFG_PRIO_NBR, 677 /* USER CODE END CFG_SCH_Prio_Id_t */ 678 } CFG_SCH_Prio_Id_t; 679 680 /** 681 * This is a bit mapping over 32bits listing all events id supported in the application 682 */ 683 typedef enum 684 { 685 CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID, 686 CFG_IDLEEVT_SYSTEM_HCI_CMD_EVT_RSP_ID, 687 /* USER CODE BEGIN CFG_IdleEvt_Id_t */ 688 689 /* USER CODE END CFG_IdleEvt_Id_t */ 690 } CFG_IdleEvt_Id_t; 691 692 /****************************************************************************** 693 * LOW POWER 694 ******************************************************************************/ 695 /** 696 * Supported requester to the MCU Low Power Manager - can be increased up to 32 697 * It list a bit mapping of all user of the Low Power Manager 698 */ 699 typedef enum 700 { 701 CFG_LPM_APP, 702 CFG_LPM_APP_BLE, 703 /* USER CODE BEGIN CFG_LPM_Id_t */ 704 705 /* USER CODE END CFG_LPM_Id_t */ 706 } CFG_LPM_Id_t; 707 708 /****************************************************************************** 709 * OTP manager 710 ******************************************************************************/ 711 #define CFG_OTP_BASE_ADDRESS OTP_AREA_BASE 712 713 #define CFG_OTP_END_ADRESS OTP_AREA_END_ADDR 714 715 #endif /* APP_CONF_H */ 716
