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Searched refs:CFGR2 (Results 1 – 25 of 374) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_hal_rcc_ex.c212 …if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) in HAL_RCCEx_PeriphCLKConfig()
260 if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) in HAL_RCCEx_PeriphCLKConfig()
424 … prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; in HAL_RCCEx_GetPeriphCLKFreq()
430 if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) in HAL_RCCEx_GetPeriphCLKFreq()
434 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; in HAL_RCCEx_GetPeriphCLKFreq()
435 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; in HAL_RCCEx_GetPeriphCLKFreq()
512 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; in HAL_RCCEx_GetPeriphCLKFreq()
513 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; in HAL_RCCEx_GetPeriphCLKFreq()
537 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; in HAL_RCCEx_GetPeriphCLKFreq()
538 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; in HAL_RCCEx_GetPeriphCLKFreq()
[all …]
Dstm32f1xx_hal_rcc.c318 CLEAR_REG(RCC->CFGR2); in HAL_RCC_DeInit()
603 ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) in HAL_RCC_OscConfig()
662 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); in HAL_RCC_OscConfig()
722 SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); in HAL_RCC_OscConfig()
1116 … prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; in HAL_RCC_GetSysClockFreq()
1122 if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) in HAL_RCC_GetSysClockFreq()
1126 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; in HAL_RCC_GetSysClockFreq()
1127 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; in HAL_RCC_GetSysClockFreq()
1221 RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); in HAL_RCC_GetOscConfig()
1298 RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL); in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_rcc.c311 CLEAR_REG(RCC->CFGR2); in HAL_RCC_DeInit()
1069 if ((pClkInitStruct->APB3CLKDivider) > ((RCC->CFGR2 & RCC_CFGR2_PPRE3) >> 8)) in HAL_RCC_ClockConfig()
1072 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE3, ((pClkInitStruct->APB3CLKDivider) << 8)); in HAL_RCC_ClockConfig()
1078 if ((pClkInitStruct->APB2CLKDivider) > ((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4)) in HAL_RCC_ClockConfig()
1081 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pClkInitStruct->APB2CLKDivider) << 4)); in HAL_RCC_ClockConfig()
1088 if ((pClkInitStruct->APB1CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE1)) in HAL_RCC_ClockConfig()
1091 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pClkInitStruct->APB1CLKDivider); in HAL_RCC_ClockConfig()
1098 if ((pClkInitStruct->AHBCLKDivider) > (RCC->CFGR2 & RCC_CFGR2_HPRE)) in HAL_RCC_ClockConfig()
1101 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pClkInitStruct->AHBCLKDivider); in HAL_RCC_ClockConfig()
1204 if ((pClkInitStruct->AHBCLKDivider) < (RCC->CFGR2 & RCC_CFGR2_HPRE)) in HAL_RCC_ClockConfig()
[all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_bus.h378 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); in LL_AHB1_GRP1_EnableBusClock()
379 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); in LL_AHB1_GRP1_EnableBusClock()
489 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); in LL_AHB1_GRP1_DisableBusClock()
779 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); in LL_AHB2_GRP1_EnableBusClock()
780 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); in LL_AHB2_GRP1_EnableBusClock()
928 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); in LL_AHB2_GRP1_DisableBusClock()
1590 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); in LL_AHB2_GRP2_EnableBusClock()
1591 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); in LL_AHB2_GRP2_EnableBusClock()
1658 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); in LL_AHB2_GRP2_DisableBusClock()
1823 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); in LL_APB1_GRP1_EnableBusClock()
[all …]
Dstm32u5xx_ll_adc.h4245 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, (TriggerFrequencyMode >> 2U)); in LL_ADC_SetTriggerFrequencyMode()
4249 MODIFY_REG(ADCx->CFGR2, ADC4_CFGR2_LFTRIG, TriggerFrequencyMode); in LL_ADC_SetTriggerFrequencyMode()
4265 return (uint32_t)((READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)) << 2U); in LL_ADC_GetTriggerFrequencyMode()
4269 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC4_CFGR2_LFTRIG)); in LL_ADC_GetTriggerFrequencyMode()
4293 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode); in LL_ADC_REG_SetSamplingMode()
4308 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG)); in LL_ADC_REG_GetSamplingMode()
4328 SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG); in LL_ADC_REG_StartSamplingPhase()
4350 CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG); in LL_ADC_REG_StopSamplingPhase()
7324 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope); in LL_ADC_SetOverSamplingScope()
7328 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE, OvsScope); in LL_ADC_SetOverSamplingScope()
[all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rcc.c312 WRITE_REG(RCC->CFGR2, 0x00100000U); in HAL_RCC_DeInit()
900 if ((pRCC_ClkInitStruct->APB1CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE1)) in HAL_RCC_ClockConfig()
902 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, (pRCC_ClkInitStruct->APB1CLKDivider)); in HAL_RCC_ClockConfig()
910 if ((pRCC_ClkInitStruct->APB2CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE2)) in HAL_RCC_ClockConfig()
912 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, (pRCC_ClkInitStruct->APB2CLKDivider)); in HAL_RCC_ClockConfig()
920 if ((pRCC_ClkInitStruct->APB4CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE4)) in HAL_RCC_ClockConfig()
922 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE4, (pRCC_ClkInitStruct->APB4CLKDivider)); in HAL_RCC_ClockConfig()
930 if ((pRCC_ClkInitStruct->APB5CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE5)) in HAL_RCC_ClockConfig()
932 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE5, (pRCC_ClkInitStruct->APB5CLKDivider)); in HAL_RCC_ClockConfig()
940 if ((pRCC_ClkInitStruct->AHBCLKDivider) > (RCC->CFGR2 & RCC_CFGR2_HPRE)) in HAL_RCC_ClockConfig()
[all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc.c394 CLEAR_REG(RCC->CFGR2); in HAL_RCC_DeInit()
1398 if ((pRCC_ClkInitStruct->APB2CLKDivider) > ((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4)) in HAL_RCC_ClockConfig()
1401 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4)); in HAL_RCC_ClockConfig()
1408 if ((pRCC_ClkInitStruct->APB1CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE1)) in HAL_RCC_ClockConfig()
1411 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider); in HAL_RCC_ClockConfig()
1418 if ((pRCC_ClkInitStruct->AHBCLKDivider) > (RCC->CFGR2 & RCC_CFGR2_HPRE)) in HAL_RCC_ClockConfig()
1421 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider); in HAL_RCC_ClockConfig()
1549 if ((pRCC_ClkInitStruct->AHBCLKDivider) < (RCC->CFGR2 & RCC_CFGR2_HPRE)) in HAL_RCC_ClockConfig()
1552 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider); in HAL_RCC_ClockConfig()
1573 if ((pRCC_ClkInitStruct->APB1CLKDivider) < (RCC->CFGR2 & RCC_CFGR2_PPRE1)) in HAL_RCC_ClockConfig()
[all …]
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_rcc.h821 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)); in LL_RCC_HSE_GetPrediv2()
1183 MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U)); in LL_RCC_SetI2SClockSource()
1242 return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx); in LL_RCC_GetI2SClockSource()
1481 MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC), in LL_RCC_PLL_ConfigDomain_SYS()
1484 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1)); in LL_RCC_PLL_ConfigDomain_SYS()
1502 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC, ((PLLSource & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U)); in LL_RCC_PLL_SetMainSource()
1522 uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U); in LL_RCC_PLL_GetMainSource()
1585 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)); in LL_RCC_PLL_GetPrediv()
1665 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL3MUL, Divider | Multiplicator); in LL_RCC_PLL_ConfigDomain_PLLI2S()
1684 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL)); in LL_RCC_PLLI2S_GetMultiplicator()
[all …]
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal.h537 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
544 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
551 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
558 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2,SYSCFG_CFGR2_SPL)
564 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SPF)
568 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
586 SET_BIT(SYSCFG->CFGR2, (__PIN__));\
590 … CLEAR_BIT(SYSCFG->CFGR2, (__PIN__));\
629 SET_BIT(SYSCFG->CFGR2, (__BREAK__));\
633 CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\
Dstm32g0xx_ll_system.h1529 …MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_E… in LL_SYSCFG_SetTIMBreakInputs()
1531 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_ECCL, Break); in LL_SYSCFG_SetTIMBreakInputs()
1554 …return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL … in LL_SYSCFG_GetTIMBreakInputs()
1556 …return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_ECCL)… in LL_SYSCFG_GetTIMBreakInputs()
1567 return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)) ? 1UL : 0UL); in LL_SYSCFG_IsActiveFlag_SP()
1577 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF); in LL_SYSCFG_ClearFlag_SP()
1604 SET_BIT(SYSCFG->CFGR2, ConfigClampingDiode); in LL_SYSCFG_EnableClampingDiode()
1630 CLEAR_BIT(SYSCFG->CFGR2, ConfigClampingDiode); in LL_SYSCFG_DisableClampingDiode()
1655 return ((READ_BIT(SYSCFG->CFGR2, ConfigClampingDiode) == (ConfigClampingDiode)) ? 1UL : 0UL); in LL_SYSCFG_IsEnabledClampingDiode()
Dstm32g0xx_ll_adc.h2243 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource); in LL_ADC_SetClock()
2267 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); in LL_ADC_GetClock()
2515 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode); in LL_ADC_SetTriggerFrequencyMode()
2528 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)); in LL_ADC_GetTriggerFrequencyMode()
4380 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope); in LL_ADC_SetOverSamplingScope()
4393 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); in LL_ADC_GetOverSamplingScope()
4416 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont); in LL_ADC_SetOverSamplingDiscont()
4435 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS)); in LL_ADC_GetOverSamplingDiscont()
4472 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); in LL_ADC_ConfigOverSamplingRatioShift()
4491 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); in LL_ADC_GetOverSamplingRatio()
[all …]
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal.h485 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
491 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CCL)
499 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
506 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2,SYSCFG_CFGR2_SPL)
517 …((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__)) != 0U) ? 1U …
528 SET_BIT(SYSCFG->CFGR2, (__FLAG__));\
581 SET_BIT(SYSCFG->CFGR2, (__BREAK__));\
585 CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\
Dstm32u0xx_ll_adc.h2196 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource); in LL_ADC_SetClock()
2220 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); in LL_ADC_GetClock()
2468 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode); in LL_ADC_SetTriggerFrequencyMode()
2481 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)); in LL_ADC_GetTriggerFrequencyMode()
4312 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope); in LL_ADC_SetOverSamplingScope()
4325 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); in LL_ADC_GetOverSamplingScope()
4348 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont); in LL_ADC_SetOverSamplingDiscont()
4367 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS)); in LL_ADC_GetOverSamplingDiscont()
4404 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); in LL_ADC_ConfigOverSamplingRatioShift()
4423 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); in LL_ADC_GetOverSamplingRatio()
[all …]
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal.h410 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
411 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
426 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
427 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
442 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK);…
443 … SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
457 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF)
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dsystem_stm32f1xx.c264 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; in SystemCoreClockUpdate()
300 prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; in SystemCoreClockUpdate()
301 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; in SystemCoreClockUpdate()
312 prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; in SystemCoreClockUpdate()
313 pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; in SystemCoreClockUpdate()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_bus.h411 SET_BIT(RCC->CFGR2, AHBx); in LL_AHB_DisableClock()
430 CLEAR_BIT(RCC->CFGR2, AHBx); in LL_AHB_EnableClock()
432 tmpreg = READ_BIT(RCC->CFGR2, AHBx); in LL_AHB_EnableClock()
451 return ((READ_BIT(RCC->CFGR2, AHBx) == AHBx) ? 1UL : 0UL); in LL_AHB_IsDisabledClock()
474 SET_BIT(RCC->CFGR2, APBx); in LL_APB_DisableClock()
491 CLEAR_BIT(RCC->CFGR2, APBx); in LL_APB_EnableClock()
493 tmpreg = READ_BIT(RCC->CFGR2, APBx); in LL_APB_EnableClock()
510 return ((READ_BIT(RCC->CFGR2, APBx) == APBx) ? 1UL : 0UL); in LL_APB_IsDisabledClock()
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_system.h354 CLEAR_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN); in LL_SYSCFG_EnableFirewall()
364 return !(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN) == SYSCFG_CFGR2_FWDISEN); in LL_SYSCFG_IsEnabledFirewall()
388 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CAPA, IoPinConnect); in LL_SYSCFG_SetVLCDRailConnection()
411 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CAPA)); in LL_SYSCFG_GetVLCDRailConnection()
433 SET_BIT(SYSCFG->CFGR2, ConfigFastModePlus); in LL_SYSCFG_EnableFastModePlus()
454 CLEAR_BIT(SYSCFG->CFGR2, ConfigFastModePlus); in LL_SYSCFG_DisableFastModePlus()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal.h393 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
399 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
405 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
411 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
420 …SCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_CCMBSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\
425 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal.h435 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
441 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
447 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
453 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
462 …FG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\
467 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_adc.h1928 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource); in LL_ADC_SetClock()
1952 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); in LL_ADC_GetClock()
2200 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode); in LL_ADC_SetTriggerFrequencyMode()
2213 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)); in LL_ADC_GetTriggerFrequencyMode()
4054 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope); in LL_ADC_SetOverSamplingScope()
4067 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); in LL_ADC_GetOverSamplingScope()
4090 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont); in LL_ADC_SetOverSamplingDiscont()
4109 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS)); in LL_ADC_GetOverSamplingDiscont()
4146 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); in LL_ADC_ConfigOverSamplingRatioShift()
4165 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); in LL_ADC_GetOverSamplingRatio()
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/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal.h499 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
505 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
511 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
517 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
526 …__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0…
530 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_rcc.c260 CLEAR_REG(RCC->CFGR2); in HAL_RCC_DeInit()
1103 tmpreg1 = RCC->CFGR2; in HAL_RCC_ClockConfig()
1143 RCC->CFGR2 = tmpreg1; in HAL_RCC_ClockConfig()
1168 …SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_… in HAL_RCC_ClockConfig()
1306 …SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_… in HAL_RCC_GetHCLKFreq()
1319 …return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_P… in HAL_RCC_GetPCLK1Freq()
1331 …return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE2) >> RCC_CFGR2_PPRE2_P… in HAL_RCC_GetPCLK2Freq()
1535 tmpreg1 = RCC->CFGR2; in HAL_RCC_GetClockConfig()
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_rcc.h1672 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, ADCxSource); in LL_RCC_SetADCClockSource()
1714 MODIFY_REG(RCC->CFGR2, (ADCxSource >> 16U), (ADCxSource & 0x0000FFFFU)); in LL_RCC_SetADCClockSource()
1716 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, ADCxSource); in LL_RCC_SetADCClockSource()
1986 return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx)); in LL_RCC_GetADCClockSource()
2032 return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx) | (ADCx << 16U)); in LL_RCC_GetADCClockSource()
2034 return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx)); in LL_RCC_GetADCClockSource()
2245 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); in LL_RCC_PLL_ConfigDomain_SYS()
2294 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV)); in LL_RCC_PLL_ConfigDomain_SYS()
2381 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)); in LL_RCC_PLL_GetPrediv()
Dstm32f3xx_hal.h733 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
734 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
749 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
750 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
765 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK);…
766 … SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_ll_adc.h2205 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource); in LL_ADC_SetClock()
2229 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); in LL_ADC_GetClock()
2477 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode); in LL_ADC_SetTriggerFrequencyMode()
2490 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)); in LL_ADC_GetTriggerFrequencyMode()
4402 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope); in LL_ADC_SetOverSamplingScope()
4415 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); in LL_ADC_GetOverSamplingScope()
4438 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont); in LL_ADC_SetOverSamplingDiscont()
4457 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS)); in LL_ADC_GetOverSamplingDiscont()
4494 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); in LL_ADC_ConfigOverSamplingRatioShift()
4513 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); in LL_ADC_GetOverSamplingRatio()
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