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Searched refs:C2IMR1 (Results 1 – 25 of 62) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_hal_rtc_ex.h626 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVE…
627 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_E…
727 #define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
728 #define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVEN…
1009 #define __HAL_RTC_TAMPER_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
1010 #define __HAL_RTC_TAMPER_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
1092 #define __HAL_RTC_SSRU_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_SSRU_EVENT)
1093 #define __HAL_RTC_SSRU_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_SSRU_EVENT))
Dstm32wlxx_hal_lptim.h581 #define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->C2IMR1\
583 #define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->C2IMR1\
586 #define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->C2IMR1\
588 #define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->C2IMR1\
591 #define __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT() (EXTI->C2IMR1\
593 #define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT() (EXTI->C2IMR1\
Dstm32wlxx_ll_exti.h312 SET_BIT(EXTI->C2IMR1, ExtiLine); in LL_C2_EXTI_EnableIT_0_31()
454 CLEAR_BIT(EXTI->C2IMR1, ExtiLine); in LL_C2_EXTI_DisableIT_0_31()
596 return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); in LL_C2_EXTI_IsEnabledIT_0_31()
Dstm32wlxx_ll_system.h921 CLEAR_BIT(SYSCFG->C2IMR1, Interrupt); in LL_C2_SYSCFG_GRP1_EnableIT()
1001 SET_BIT(SYSCFG->C2IMR1, Interrupt); in LL_C2_SYSCFG_GRP1_DisableIT()
1082 return ((READ_BIT(SYSCFG->C2IMR1, Interrupt) != (Interrupt)) ? 1UL : 0UL); in LL_C2_SYSCFG_GRP1_IsEnabledIT()
Dstm32wlxx_hal_rtc.h721 #define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
722 #define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_comp.c456 SET_BIT(EXTI->C2IMR1, exti_line); in HAL_COMP_Init()
460 CLEAR_BIT(EXTI->C2IMR1, exti_line); in HAL_COMP_Init()
469 CLEAR_BIT(EXTI->C2IMR1, exti_line); in HAL_COMP_Init()
908 CLEAR_BIT(EXTI->C2IMR1, COMP_GET_EXTI_LINE(hcomp->Instance)); in HAL_COMP_Stop_IT()
Dstm32h7xx_hal_exti.c288 regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); in HAL_EXTI_SetConfigLine()
422 regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); in HAL_EXTI_GetConfigLine()
547 regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); in HAL_EXTI_ClearConfigLine()
Dstm32h7xx_ll_exti.c130 LL_EXTI_WriteReg(C2IMR1, 0x00000000U); in LL_EXTI_DeInit()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_hal_gpio.c255 temp = EXTI->C2IMR1; in HAL_GPIO_Init()
265 EXTI->C2IMR1 = temp; in HAL_GPIO_Init()
326 EXTI->C2IMR1 &= ~(iocurrent); in HAL_GPIO_DeInit()
Dstm32wlxx_hal_exti.c223 regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); in HAL_EXTI_SetConfigLine()
302 regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); in HAL_EXTI_GetConfigLine()
399 regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); in HAL_EXTI_ClearConfigLine()
Dstm32wlxx_ll_exti.c108 LL_EXTI_WriteReg(C2IMR1, 0x00000000U); in LL_EXTI_DeInit()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_hal_rtc_ex.h479 #define __HAL_RTC_WAKEUPTIMER_EXTIC2_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_E…
485 #define __HAL_RTC_WAKEUPTIMER_EXTIC2_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER…
915 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_TAMPER_TI…
927 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_TAMPER_…
Dstm32wbxx_ll_exti.h367 SET_BIT(EXTI->C2IMR1, ExtiLine); in LL_C2_EXTI_EnableIT_0_31()
505 CLEAR_BIT(EXTI->C2IMR1, ExtiLine); in LL_C2_EXTI_DisableIT_0_31()
643 return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); in LL_C2_EXTI_IsEnabledIT_0_31()
Dstm32wbxx_ll_system.h1234 CLEAR_BIT(SYSCFG->C2IMR1, Interrupt); in LL_C2_SYSCFG_GRP1_EnableIT()
1318 SET_BIT(SYSCFG->C2IMR1, Interrupt); in LL_C2_SYSCFG_GRP1_DisableIT()
1402 return ((READ_BIT(SYSCFG->C2IMR1, Interrupt) != (Interrupt)) ? 1UL : 0UL); in LL_C2_SYSCFG_GRP1_IsEnabledIT()
Dstm32wbxx_hal_rtc.h672 #define __HAL_RTC_ALARM_EXTIC2_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
684 #define __HAL_RTC_ALARM_EXTIC2_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_exti.c253 regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); in HAL_EXTI_SetConfigLine()
342 regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); in HAL_EXTI_GetConfigLine()
437 regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); in HAL_EXTI_ClearConfigLine()
Dstm32mp1xx_ll_exti.c111 LL_EXTI_WriteReg(C2IMR1, 0xFFFE0000U); in LL_EXTI_DeInit()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_exti.h335 SET_BIT(EXTI->C2IMR1, ExtiLine); in LL_EXTI_EnableIT_0_31()
446 CLEAR_BIT(EXTI->C2IMR1, ExtiLine); in LL_EXTI_DisableIT_0_31()
557 return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); in LL_EXTI_IsEnabledIT_0_31()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_exti.h764 SET_BIT(EXTI->C2IMR1, ExtiLine); in LL_C2_EXTI_EnableIT_0_31()
888 CLEAR_BIT(EXTI->C2IMR1, ExtiLine); in LL_C2_EXTI_DisableIT_0_31()
1013 return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); in LL_C2_EXTI_IsEnabledIT_0_31()
Dstm32h7xx_hal_rcc_ex.h3639 #define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
3645 #define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/src/
Dstm32wbxx_ll_exti.c108 LL_EXTI_WriteReg(C2IMR1, 0x00000000U); in LL_EXTI_DeInit()
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb50xx.h536 …__IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status regis… member
693 …__IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Addre… member
Dstm32wb1mxx.h531 …__IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status regis… member
709 …__IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Addre… member
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h521 …__IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status regis… member
699 …__IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Addre… member
Dstm32wb15xx.h531 …__IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status regis… member
709 …__IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Addre… member

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