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Searched refs:C2CR3 (Results 1 – 19 of 19) sorted by relevance

/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_pwr.h1422 MODIFY_REG(PWR->C2CR3, PWR_C2CR3_EWRFBUSY, RadioBusyTrigger); in LL_C2_PWR_SetRadioBusyTrigger()
1436 return (uint32_t)(READ_BIT(PWR->C2CR3, PWR_C2CR3_EWRFBUSY)); in LL_C2_PWR_GetRadioBusyTrigger()
1450 MODIFY_REG(PWR->C2CR3, PWR_C2CR3_EWRFIRQ, RadioIRQTrigger); in LL_C2_PWR_SetRadioIRQTrigger()
1463 return (uint32_t)(READ_BIT(PWR->C2CR3, PWR_C2CR3_EWRFIRQ)); in LL_C2_PWR_GetRadioIRQTrigger()
1613 SET_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL); in LL_C2_PWR_EnableInternWU()
1623 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL); in LL_C2_PWR_DisableInternWU()
1633 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL) == (PWR_C2CR3_EIWUL)) ? 1UL : 0UL); in LL_C2_PWR_IsEnabledInternWU()
1649 SET_BIT(PWR->C2CR3, WakeUpPin); in LL_C2_PWR_EnableWakeUpPin()
1665 CLEAR_BIT(PWR->C2CR3, WakeUpPin); in LL_C2_PWR_DisableWakeUpPin()
1681 return ((READ_BIT(PWR->C2CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_C2_PWR_IsEnabledWakeUpPin()
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/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_pwr.h1747 SET_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL); in LL_C2_PWR_EnableInternWU()
1757 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL); in LL_C2_PWR_DisableInternWU()
1767 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL) == (PWR_C2CR3_EIWUL)) ? 1UL : 0UL); in LL_C2_PWR_IsEnabledInternWU()
1789 SET_BIT(PWR->C2CR3, WakeUpPin); in LL_C2_PWR_EnableWakeUpPin()
1811 CLEAR_BIT(PWR->C2CR3, WakeUpPin); in LL_C2_PWR_DisableWakeUpPin()
1833 return ((READ_BIT(PWR->C2CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_C2_PWR_IsEnabledWakeUpPin()
1843 SET_BIT(PWR->C2CR3, PWR_C2CR3_APC); in LL_C2_PWR_EnablePUPDCfg()
1853 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_APC); in LL_C2_PWR_DisablePUPDCfg()
1863 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_APC) == (PWR_C2CR3_APC)) ? 1UL : 0UL); in LL_C2_PWR_IsEnabledPUPDCfg()
2633 SET_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP); in LL_C2_PWR_EnableIT_BLEWU()
[all …]
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_hal_pwr_ex.c187 SET_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL); in HAL_PWREx_EnableInternalWakeUpLine()
200 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL); in HAL_PWREx_DisableInternalWakeUpLine()
494 SET_BIT(PWR->C2CR3, PWR_C2CR3_APC); in HAL_PWREx_EnablePullUpPullDownConfig()
509 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_APC); in HAL_PWREx_DisablePullUpPullDownConfig()
Dstm32wlxx_hal_pwr.c110 LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE); in HAL_PWR_DeInit()
431 SET_BIT(PWR->C2CR3, (PWR_C2CR3_EWUP & WakeUpPinPolarity)); in HAL_PWR_EnableWakeUpPin()
452 CLEAR_BIT(PWR->C2CR3, (PWR_C2CR3_EWUP & WakeUpPinx)); in HAL_PWR_DisableWakeUpPin()
Dstm32wlxx_ll_pwr.c99 LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE); in LL_PWR_DeInit()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/src/
Dstm32wbxx_ll_pwr.c106 LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE); in LL_PWR_DeInit()
Dstm32wbxx_hal_pwr.c125 LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE); in HAL_PWR_DeInit()
Dstm32wbxx_hal_pwr_ex.c985 SET_BIT(PWR->C2CR3, (PWR_C2CR3_EWUP & WakeUpPinPolarity)); in HAL_PWREx_EnableWakeUpPin()
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb50xx.h385 …__IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset:… member
Dstm32wb1mxx.h380 …__IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset:… member
Dstm32wb30xx.h384 …__IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset:… member
Dstm32wb35xx.h415 …__IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset:… member
Dstm32wb55xx.h419 …__IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset:… member
Dstm32wb5mxx.h419 …__IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset:… member
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h370 …__IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset:… member
Dstm32wb15xx.h380 …__IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset:… member
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wl5mxx.h649 …__IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset:… member
Dstm32wl54xx.h649 …__IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset:… member
Dstm32wl55xx.h649 …__IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset:… member