Home
last modified time | relevance | path

Searched refs:BDMA_IFCR_CTCIF5_Pos (Results 1 – 22 of 22) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h6507 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6508 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h7b0xx.h6761 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6762 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h7b0xxq.h6762 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6763 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h7a3xxq.h6508 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6509 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h7b3xx.h6761 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6762 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h7b3xxq.h6762 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6763 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h730xxq.h7053 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
7054 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h733xx.h7052 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
7053 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h725xx.h6799 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6800 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h730xx.h7052 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
7053 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h735xx.h7053 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
7054 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h742xx.h6525 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6526 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h723xx.h6798 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6799 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h750xx.h6813 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6814 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h753xx.h6813 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6814 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h745xx.h6727 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6728 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h745xg.h6727 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6728 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h743xx.h6620 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6621 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h755xx.h6920 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6921 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h757xx.h7003 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
7004 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h747xg.h6810 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6811 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
Dstm32h747xx.h6810 #define BDMA_IFCR_CTCIF5_Pos (21U) macro
6811 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */