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Searched refs:APB1RSTR1 (Results 1 – 25 of 92) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_rcc.h1761 #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
1763 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
1765 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
1767 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
1770 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
1773 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
1775 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
1777 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
1779 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
1781 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
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Dstm32g4xx_ll_bus.h1141 SET_BIT(RCC->APB1RSTR1, Periphs); in LL_APB1_GRP1_ForceReset()
1211 CLEAR_BIT(RCC->APB1RSTR1, Periphs); in LL_APB1_GRP1_ReleaseReset()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_rcc.h2439 WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFUL); \
2443 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
2446 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
2450 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
2454 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
2457 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
2460 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
2464 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
2468 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
2472 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
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Dstm32l4xx_ll_bus.h1346 SET_BIT(RCC->APB1RSTR1, Periphs); in LL_APB1_GRP1_ForceReset()
1428 CLEAR_BIT(RCC->APB1RSTR1, Periphs); in LL_APB1_GRP1_ReleaseReset()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_rcc.h1815 WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFUL); \
1819 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
1821 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
1823 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
1825 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
1827 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
1829 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
1831 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
1833 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
1835 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
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Dstm32l5xx_ll_bus.h1131 SET_BIT(RCC->APB1RSTR1, Periphs); in LL_APB1_GRP1_ForceReset()
1209 CLEAR_BIT(RCC->APB1RSTR1, Periphs); in LL_APB1_GRP1_ReleaseReset()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_rcc.h2417 WRITE_REG(RCC->APB1RSTR1, 0xC8FFC3FFUL); \
2421 WRITE_REG(RCC->APB1RSTR1, 0UL); \
2425 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
2426 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
2428 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
2429 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
2431 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
2432 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
2434 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
2435 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
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Dstm32h7rsxx_ll_bus.h1599 SET_BIT(RCC->APB1RSTR1, Periphs); in LL_APB1_GRP1_ForceReset()
1659 CLEAR_BIT(RCC->APB1RSTR1, Periphs); in LL_APB1_GRP1_ReleaseReset()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_rcc.h2895 WRITE_REG(RCC->APB1RSTR1, 0x027E403FU); \
2899 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
2901 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
2903 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
2905 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
2907 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
2909 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
2911 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
2914 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
2917 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
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Dstm32u5xx_ll_bus.h2091 SET_BIT(RCC->APB1RSTR1, Periphs); in LL_APB1_GRP1_ForceReset()
2159 CLEAR_BIT(RCC->APB1RSTR1, Periphs); in LL_APB1_GRP1_ReleaseReset()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_hal_rcc.h1289 WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU); \
1292 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
1294 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
1297 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
1300 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
1307 WRITE_REG(RCC->APB1RSTR1, 0x00000000U); \
1310 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
1312 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
1315 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
1318 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
Dstm32wbaxx_ll_bus.h1142 SET_BIT(RCC->APB1RSTR1, Periphs); in LL_APB1_GRP1_ForceReset()
1176 CLEAR_BIT(RCC->APB1RSTR1, Periphs); in LL_APB1_GRP1_ReleaseReset()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_bus.h1083 SET_BIT(RCC->APB1RSTR1, Periphs); in LL_APB1_GRP1_ForceReset()
1127 CLEAR_BIT(RCC->APB1RSTR1, Periphs); in LL_APB1_GRP1_ReleaseReset()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_bus.h1064 SET_BIT(RCC->APB1RSTR1, Periphs); in LL_APB1_GRP1_ForceReset()
1109 CLEAR_BIT(RCC->APB1RSTR1, Periphs); in LL_APB1_GRP1_ReleaseReset()
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h535 …__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, … member
Dstm32wle5xx.h535 …__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, … member
Dstm32wl5mxx.h676 …__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, … member
Dstm32wl54xx.h676 …__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, … member
Dstm32wl55xx.h676 …__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, … member
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h572 …__IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Low Register Address … member
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb50xx.h407 …__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, … member
Dstm32wb1mxx.h402 …__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, … member
Dstm32wb30xx.h406 …__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, … member
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h392 …__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, … member
Dstm32wb15xx.h402 …__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, … member

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