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Searched refs:AHB1ENR (Results 1 – 25 of 177) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc_ex.h972 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
974 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
979 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
981 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
986 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
988 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
993 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
995 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
1000 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
1002 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
[all …]
Dstm32f4xx_hal_rcc.h386 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
388 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
393 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
395 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
400 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
402 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
407 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
409 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
414 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
416 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
[all …]
Dstm32f4xx_ll_bus.h412 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
414 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
475 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
535 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_rcc.h412 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
414 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
419 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
421 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
426 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
428 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
433 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
435 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
440 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
442 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
[all …]
Dstm32f2xx_hal_rcc_ex.h123 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
125 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
130 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
132 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
137 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
139 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
144 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
146 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
150 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
151 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
[all …]
Dstm32f2xx_ll_bus.h241 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
243 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
294 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
344 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h589 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
591 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
597 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
599 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
605 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
607 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
613 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
615 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
621 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
623 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
[all …]
Dstm32f7xx_hal_rcc.h409 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
411 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
417 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
419 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
423 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
424 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
487 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
488 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
490 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
491 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)
Dstm32f7xx_ll_bus.h312 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
314 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
373 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
431 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_rcc.h677 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
679 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
684 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
686 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
691 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
693 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
698 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
700 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
705 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
707 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_rcc.h734 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
736 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
742 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \
744 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \
751 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
753 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
761 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
763 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
770 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
772 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
[all …]
Dstm32h5xx_ll_bus.h563 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
565 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
607 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
648 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_rcc.h972 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
974 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
980 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
982 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
988 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
990 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
997 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
999 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
1007 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
1009 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
[all …]
Dstm32h7xx_ll_bus.h875 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
877 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
914 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); in LL_AHB1_GRP1_IsEnabledClock()
950 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
3582 SET_BIT(RCC_C1->AHB1ENR, Periphs); in LL_C1_AHB1_GRP1_EnableClock()
3584 tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs); in LL_C1_AHB1_GRP1_EnableClock()
3621 return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C1_AHB1_GRP1_IsEnabledClock()
3657 CLEAR_BIT(RCC_C1->AHB1ENR, Periphs); in LL_C1_AHB1_GRP1_DisableClock()
5383 SET_BIT(RCC_C2->AHB1ENR, Periphs); in LL_C2_AHB1_GRP1_EnableClock()
5385 tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs); in LL_C2_AHB1_GRP1_EnableClock()
[all …]
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_hal_rcc.h570 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
572 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
578 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
580 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
586 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
588 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
595 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
597 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
604 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \
606 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \
[all …]
Dstm32wbaxx_ll_bus.h237 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
239 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
267 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
294 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_rcc.h518 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
520 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
526 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
528 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
534 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
536 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
542 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
544 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
550 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
552 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
[all …]
Dstm32g4xx_ll_bus.h246 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
248 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
273 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
297 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_rcc.h654 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
656 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
662 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
664 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
670 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
672 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
677 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
679 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
685 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
687 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
[all …]
Dstm32l5xx_ll_bus.h224 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
226 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
251 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
276 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_rcc.h639 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
641 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
647 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
649 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
656 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
658 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
665 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
667 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
673 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
675 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
[all …]
Dstm32l4xx_ll_bus.h330 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
332 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
361 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
389 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_rcc.h823 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN);\
825 tmpreg = READ_REG(RCC->AHB1ENR);\
831 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
833 tmpreg = READ_REG(RCC->AHB1ENR);\
840 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
842 tmpreg = READ_REG(RCC->AHB1ENR);\
848 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
850 tmpreg = READ_REG(RCC->AHB1ENR);\
856 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
858 tmpreg = READ_REG(RCC->AHB1ENR);\
[all …]
Dstm32h7rsxx_ll_bus.h325 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
327 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
356 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); in LL_AHB1_GRP1_IsEnabledClock()
384 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dsystem_stm32f4xx.c287 RCC->AHB1ENR |= 0x000001F8; in SystemInit_ExtMemCtl()
290 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); in SystemInit_ExtMemCtl()
457 RCC->AHB1ENR |= 0x0000007D; in SystemInit_ExtMemCtl()
461 RCC->AHB1ENR |= 0x000001F8; in SystemInit_ExtMemCtl()
464 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); in SystemInit_ExtMemCtl()
649 RCC->AHB1ENR |= 0x00000078; in SystemInit_ExtMemCtl()
651 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); in SystemInit_ExtMemCtl()

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