Searched refs:ADC_SMPR0_REGOFFSET (Results 1 – 1 of 1) sorted by relevance
214 #define ADC_SMPR0_REGOFFSET 0x28000000U /* SMPR0 register offset from SMPR1 is 20 … macro215 …FSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET | ADC_SMPR3_REGOFFSET | ADC_SMPR0_REGOFFSET)293 #define ADC_CHANNEL_30_SMP (ADC_SMPR0_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFF…294 #define ADC_CHANNEL_31_SMP (ADC_SMPR0_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFF…1370 …(ADC_SMPR0_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 30U))) << ADC_CHANNEL_SMPx_BITOFFSET…
